Working on codesign and optimization of chiplets, package and PCB for improvement in Signal and Power Integrity under Professor Rosenbaum in Circuits group.

• Worked on disaggregation of IBM’s AI accelerator SoC into chiplets and integration of the chiplets in anadvanced package.• Designed RTL for the transport layer so that data transferred between chiplets using UCIe interface adheres to the AXI protocol.

• Performed a complete signal integrity study for Direct Bonded Heterogeneous Integration (DBHi), an IBM proprietary silicon bridge.• Designed and analyzed multiple Universal Chiplet Interconnect Express (UCIe) modules to meet UCIe 1.1 specifications.

• Performed signal integrity and power integrity analysis on Bunch-of-Wires (BoW) interconnects for inter-chiplet communication.• Analyzed the effect of variation in power delivery network on signal integrity of these data lines.• Analyzed the effect of package design on BoW performance.• Validated BoW as a low power solution for die-to-die (D2D) interfacing.

Working in Circuits Group on Optimization of Power Delivery Network to heterogeneous integration of various chiplets.

• Worked in the Physical design team on different aspects from synthesis to place & route to floor planningof discrete and integrated graphics chips.• Worked on Full Chip Formal Equivalence Verification of all partitions in multiple sections of the latest complexfoveros design with multiple RTL churns and complex spine structures.

• Wrote tests in C++ to verify the transfer of data from different I/O devices in boot scenario.• Worked on optimization of software and hardware verification of boot architecture.• Wrote Python scripts to optimize the debugging of test failures.

Designed a Single Ended and Differential Passive RF Impedance Tuners For 2.4 GHz ISM band ApplicationsI worked on the design of two electronically tunable passive RF impedance tuners operating between 2.4 GHz and 2.5 GHz. Theoretical analysis and simulation were performed on two pi matching networks in cascade which helped in increasing the load voltage standing wave ratio (VSWR) coverage. The linearity of the optimized single ended matching network was improved by converting it into a differential structure. Both the impedance tuners based on this theory were fabricated on a two layered FR4 PCB. The fabricated single ended tuner was tested for load impedance variation up to VSWR ≤ 9.5 wherein insertion loss stayed between 0.4 dB and 5.1 dB. The differential network was tested for load impedances up to VSWR ≤ 6 wherein an insertion loss between 0.6 dB and 6.1 dB was obtained. The measured IIP3 of the differential and single ended networks were 37.4 dBm and 34.2 dBm respectively.

IGCAR – It is one of the premier nuclear research centres having the only prototype fast breeder reactor in India.· Designed and developed a turbidity meter using pulsating sensors.o IGCAR uses instruments developed in its own premises. Turbidity is a major safety standard when it comes tocoolants in type 1 nuclear reactor. Turbidity meter developed, was a basic model, which could be installed in thereactor to keep a check on turbidity values.· Prepared a layout for fabrication and also conducted preliminary calibration on different samples.o Added additional features to the device like data logging using an SD card, real time clock, interfaced it to acomputer using USB and correlated the frequency measured to turbidity values with the help of a standardturbidity meter. Frequency was measured with an accuracy of 99.98% up to 500 KHz.

· Managed the academics and curriculum of class 11 students and trained them for competitive exams.· Average score of students in class 11 increased from 78% to 83%, retention rate of students in school increasedby 21 %.