Ramya J Email & Phone Number

Design and verification engineer trained at Maven silicon, Bengaluru. Skills: Digital electronics, System Verilog, Universal Verification Methodology(UVM), Linux, Perl.Digital:Strong knowledge in areas of Number Systems and codes, Logic circuits,Combinational and Sequential circuits, FSM, Memories.Verilog:Good understanding of Data types, Operators, BA & NBA, Delays in Verilog,begin - end & fork join blocks, looping & branching construct, System tasks&Functions, compiler directives and Advanced Verilog & Code Coverage.System Verilog:Competent in areas of Memories, Interface, OOPS, Constraint Randomization,Threads, Functional coverage and regression testing.System Verilog Assertion:Comprehensive Knowledge in assertions and its types, buildingblocks, Clock definitions , System function, sequences, operators, sequencecompositions and assertion Coverage.UVM:Proficient in places of UVM Objects & Components, Factory & overridingmethods, Stimulus Modelling, Phases, Configuration, TLM, Sequence, virtualsequence & sequencer, Introduction to RAL.

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  Rns Institute Of Technology - India

  Electrical And Electronics Engineering