Contract programming for Ausdia Design Automation. Project: SDC constraint conflict detection. Implemented capability to check SDC constraints for conflicts. Detects and reports all manner of path constraint conflicts (false path vs. multi-cycle path, clock group vs. max delay) for both setup and hold. Exceedingly efficient code: can check a 5 million instance design with several hundred thousand SDC constraints and several hundred clocks in under 10 minutes, using only a few hundred megabytes of memory. Ausdia now has the industry leading constraint conflict detection capability. It is the only solution which can handle designs of hundreds of millions of instances and thousands of clocks.Project: For Ausdia Design Automation. Implemented the capability totake two revisions of the same design, and compare their verilog and their SDC files to determine the impact of the change. Reports timing paths which got either easier to meet timing on (e.g. a max_delay path was turned into a false path) or harder to meet (e.g. two clocks which were in a clock group but were changed to a multi-cycle path). Impact: This functionality allows Ausdia's customers to quickly evaluate "what if" scenarios: e.g. determine whether some IP or features could be added or changed without adversely impacting convergence. Ultra-efficient algorithms and data structures allow these decisions to be done in hours instead of weeks, even on designs with millions of instances and thousands of clocks.Project:Did programming and worked with artists, domain experts, and contract programmers to produce the an iphone ap, "Ask God" a fun program which lets the user find selected Bible verses on various topics. Integrates with Twitter and facebook, allowing the users to share their verses with their friends on social media sites.

Tradebook Post-Trade, clearing.

Maintained and enhanced Zroute. Implemented threshold-based nondefault rules and advanced soft design rule support, which improve both DRC convergence and route quality.

Enhanced the global router for Mentor's Olympus-SOC. Implemented more accurate capacity calculation which had a dramatic impact on the runtime and route quality (drcs and wirelength) of track and detailed routing.

Created a detailed routing engine, tightly integrated with a timer, optimizer, and clock-tree synthesizer, creating an industry-leading performance-driven routing solution.

Implemented a truly gridless, any wire/any width,performance-driven detailed router in C++.Research and Development of new algorithms for congestionanalysis, rip-up and reroute in the detailed router.