Tej P. Email and Phone Number
7.10 year of working experience in ASIC Verification.Experience in building (or enhancing) verification environment from scratch using Verilog, System Verilog and methodologies like UVM.Good knowledge in HDMI, AMBA (i.e., CHI, AXI, AXI-S, AHB, APB) Protocols. Basic knowledge in Ethernet. Shallow knowledge in PCIe, ACE, I2C, SPI.Have worked on SoC, NoC, Sub-system, IP level verification environment.Been part of projects cycle with Tap-out in which handling different tasks of verifications.Good understanding of ASIC design flow and design verification techniques.
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Ip Verification EngineerIntel Corporation May 2024 - PresentNetwork Group -
Fpga Ip Software Development EngineerIntel Corporation May 2022 - Apr 2024India -
Senior Verification EngineerTech Mahindra Cerium Pvt Ltd Dec 2021 - Apr 2022 -
Verification EngineerPerfectvips Dec 2018 - Nov 2021India -
Verification EngineerEinfochips (An Arrow Company) Jan 2017 - Nov 2018India -
Engineering TraineeEinfochips (An Arrow Company) Jul 2016 - Dec 2016India
Tej P. Education Details
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Electrical, Electronics And Communications Engineering
Frequently Asked Questions about Tej P.
What company does Tej P. work for?
Tej P. works for Intel Corporation
What is Tej P.'s role at the current company?
Tej P.'s current role is Senior ASIC Design Verification Engineer @ INTEL.
What schools did Tej P. attend?
Tej P. attended A D Patel Institute Of Technology, Cvm University.
Who are Tej P.'s colleagues?
Tej P.'s colleagues are Akshatha Chandrashekar, Narahari Murthy Narasimhaiah, Noah Mcdaniel, Aoife Barnicle, Lihi Arbuz, Natali Ziharev, S K Murthy.
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