Randy Posey Email & Phone Number

Austin

• Wrote compiler code for of 14nm 2 read/2 write RF (register file) cells to build arrays up to 512 entries and 144 bits in size, both netlist creation and layout placement. The design included power gating, multiple power supplies, and write masking.• Created additional decoder, read/write latch, and power gating cells as needed.• Worked with mask designers to find and fix LVS, DRC, ERC, DFM, noise, EM, IR, issues in layout.

Austin, Texas Area

• Optimized a 20nm high density/low power compiler design which included options for BIST, redundancy, power gating, write thru, write masking, muxing 2/4/8/16 sets of bitlines.• Ran verification of compiler design for all different sizes, options, and timing corners. This included SPICE margin analysis to check for setup/hold/ClockToQ issues, emir analysis, library model characterization, and working with mask design on DRC/ERC issues.

Austin, Texas Area

• Designed and ran feasibility studies for 28nm and 20nm 6T SRAM and register file memories which incorporated mixed VT decoders with power gating, memory cell power gating, and floating bitlines to reduce array power.• Evaluated senseamp and full-rail memory structures for optimum design of area, power, speed, and reliability in 20nm and 28nm technology.

Austin, Texas Area

• Designed 256KB L2 Data sense-amp SRAM for 32nm core used in a high performance computing server processor which included decoder power gating, DVFS (Dynamic Voltage Frequency Scaling), floating bitlines, drowsy and sleep modes for reducing array power.• Wrote Verilog HDL models for RAM, ROM, register file, and PLL designs, which then were verified with formal verification to match the circuit.

• Led L2 SRAM design for 65nm project; from floor planning and definition of SRAM designs. Laid out ram column for the data ram to ensure the minimum bitline cap and area.• Designed stdcell latches, flops, and complex CMOS gates. Ran functional verification, noise, charge sharing, EM/IR design checks. Compiled library of cells.• Designed RF memory compiler to build register files with 1-4 read/write ports from individual memory, sense amp, precharge, write driver, decoder, and control logic cells.• Wrote VHDL models of RAM, ROM, and RF memory arrays including memory structures and control/test logic.• Designed sense amp RAM arrays. From feasibility, to schematic capture, floorplanning, layout, analysis of speed, read stability, writeability, coupling noise, EM/IR, charge sharing, drive strength, logical equivalence in technologies down to 45nm. Including instruction cache, tag array, branch predecoded storage.• Worked with the layout group to ensure the requirements for area, power grid, strapping of large drivers, signal shielding of important signals (clocks, wordlines, precharge lines, sense lines).• Led silicon debug of the K7 memory arrays, including tracking circuit issues (VDDmin, VDDmax, speed, ram bit failures), creating tester patterns to determine the failure and confirm the issue with spice simulations.• Designed stdcell logic including drawing schematics from rtl, placement, routing, and buffering.• Verified stdcell designs including timing closure with pathmill (static timing) LEC, IR drop, and edge rate.• Developed programs to automate design process steps including:o Circuit checker for memory arrays which included checks for: beta ratio, drive/load ratio, floating nets, and charge sharing.o Create spice PWL waveforms and tabularize spice results.o Developed program to auto-generate web pages displaying spice results with pass/fail criteria for functional races, power races, setup (speed), hold (race), delay.

Bs, Electrical Engineering (Computer Engineering Option)

Activities and Societies: Eta Kappa Nu Electrical Engineering Honor Society

Pre-Engineering