Ranjit Eswaran Email & Phone Number

Work on developing in-house EDA tools(C++, Python) using optimal data structures for runtime/memory optimization. Working with a team to build world class first-in-market products. Scalability of tools from a proof-of-concept to real sales is another challenge. Use statistical techniques for predictive reliability and build them into the tools.

Worked on C++ based DRC engines for lower nodes. The performance of a custom router on lower nodes with extremely complex rules was of paramount importance. Interpretation of the foundry rules and translation into elegant, efficient code was a fun challenge.

Leading a team on lower node testchip tapeouts. Responsibilities included IP and block integration in to fullchip, managing the deliverables through some key automation, working through unstable, first-cut collaterals and delivering the GDS to foundry. Worked on developing a C++ based optimizer to use any available timing slacks for path optimization.

Responsibilities included developing flows/runsets for Fullchip LVS, DRC, ERC et al gamut of checks necessary for tapeout. Worked on 3DIC flows and wrote a viafill deck for faster TAT on fullchip IR drop issues. Managed a team for layout and physical verification flows.

Bangalore

Was part of the acquired Zenassis EDA team. Worked on developing VB based pre-sales power calculator based on RTL inputs. Worked on SiliconSmart based standard cell characterization flows and gained expertise on characterization.

CAD engineer for routing/placement flows followed by RC-extraction, EM/IR flows. Worked on ideas for reduction in IR drop runtimes using superposition.

Ms, Electrical Engineering

E & C, Electronics And Communication

Puc

Education record