Develop new verification flowsVerification of single precision floating point using formalML using Tensorflow for compute resource optimization and intelligent test selectionPython integration with system verilog/systemc for cosimDevelop UVM methodology guidelinesAWS integartion for running simulations in on-prem and AWSTools and flows for Continuous integrationCode release flowVPI and DPI based flowsVerification plan and Coverage flow using verification plannerOptimized build flow from small blocks, subsystem and fullchipVerification dashboard and regression framework using internal and external toolsTechnical lead /manage a small team in US and offshorePresented in CDNlive and SNUG on using new verification flows

Fully architected a UVM verification Env from ground up for next generation FPGA. Developed methodology for configuring FPGA using propreitary tools and provided hooks to use that from within UVM env. Worked with other teams like software to add plugins and hooks in verification env for other teams to use this env for verification with software image downloaded to the FPGA.Integrated third party Verification IP's in UVM env and extended the env to use hundreds of VIP everything within UVM env. Also participated and recommended design management tools for company wide use. Architected design management tool wrappers and build/release/regression flows for use with in fullchip verificationTechnical lead for all fullchip verification flows, tools and envMethodolgy for coverage collections and metrics driven verification-Presented paper in SNUG12 (third best paper) and DVCon13-FPGA verification using UVM and VPI. Designer Track DAC 2013

Manager and hands on technical lead for DDR/GDDR PhyArchitected OVM env for simulataneously doing logic sim, C based tests and channel model using PythonArchitected and managed offshore BFM model developmentPresented paper in SNUG. "Mixed signal verification using AMS from UVM env"

Worked as verification consultant and implementd flows/verified design for many early and mid stage companiesWorked on OVM based methodology and assertions, coverageCloud based tool for HW design using EC2

DDR3 verification/model using denali and verilogEmbedded dram controller verification using random vectorsMethodology for denali/verilog simulation

Worked on serial interlaken protocol Developed system verilog random methodologyRandom diags and checkers for TX

Developed diags for a gaming chipBring up of the gaming chip in LAB