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Ravi Ram Email & Phone Number

AMD Fellow at AMD
Location: Sunnyvale, California, United States 15 work roles 3 schools
1 work email found @amd.com LinkedIn matched
✓ Verified Jul 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email r****@amd.com
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Current company
AMD
Role
AMD Fellow
Location
Sunnyvale, California, United States

Who is Ravi Ram? Overview

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Quick answer

Ravi Ram is listed as AMD Fellow at AMD, based in Sunnyvale, California, United States. AeroLeads shows a work email signal at amd.com and a matched LinkedIn profile for Ravi Ram.

Ravi Ram previously worked as Fellow Silicon Design Engineer at Amd and Principal Engineer, Verification and Methodology at Xilinx. Ravi Ram holds Ms, Electrical Engineering from San José State University.

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Email format at AMD

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{first}_{last}@amd.com
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AeroLeads found 1 current-domain work email signal for Ravi Ram. Compare company email patterns before reaching out.

Profile bio

About Ravi Ram

Ravi Ram is a AMD Fellow at AMD. He possess expertise in systemverilog, verilog, functional verification, asic, simulations and 12 more skills.

Listed skills include Systemverilog, Verilog, Functional Verification, Asic, and 13 others.

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Ravi Ram's current company

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AMD
Amd
AMD Fellow
Sunnyvale, California
Website
AeroLeads page
15 roles · 35 years

Ravi Ram work experience

A career timeline built from the work history available for this profile.

Fellow Silicon Design Engineer

Current
Amd

Santa Clara, California, Us

Jun 2022 - Present

Principal Engineer, Verification And Methodology

San Jose, Ca, Us

Develop new verification flowsVerification of single precision floating point using formalML using Tensorflow for compute resource optimization and intelligent test selectionPython integration with system verilog/systemc for cosimDevelop UVM methodology guidelinesAWS integartion for running simulations in on-prem and AWSTools and flows for Continuous integrationCode release flowVPI and DPI based flowsVerification plan and Coverage flow using verification plannerOptimized build flow from small blocks, subsystem and fullchipVerification dashboard and regression framework using internal and external toolsTechnical lead /manage a small team in US and offshorePresented in CDNlive and SNUG on using new verification flows

Nov 2013 - Jun 2022

Verification Architect

Altera

Fully architected a UVM verification Env from ground up for next generation FPGA. Developed methodology for configuring FPGA using propreitary tools and provided hooks to use that from within UVM env. Worked with other teams like software to add plugins and hooks in verification env for other teams to use this env for verification with software image downloaded to the FPGA.Integrated third party Verification IP's in UVM env and extended the env to use hundreds of VIP everything within UVM env. Also participated and recommended design management tools for company wide use. Architected design management tool wrappers and build/release/regression flows for use with in fullchip verificationTechnical lead for all fullchip verification flows, tools and envMethodolgy for coverage collections and metrics driven verification-Presented paper in SNUG12 (third best paper) and DVCon13-FPGA verification using UVM and VPI. Designer Track DAC 2013

Feb 2012 - Nov 2013

Principal Mts

Amd

Santa Clara, California, Us

Manager and hands on technical lead for DDR/GDDR PhyArchitected OVM env for simulataneously doing logic sim, C based tests and channel model using PythonArchitected and managed offshore BFM model developmentPresented paper in SNUG. "Mixed signal verification using AMS from UVM env"

Jul 2010 - May 2012

Design Verification Consultant

Amd

Santa Clara, California, Us

Sep 2009 - Jun 2010

Director Design Verification

Us

Worked as verification consultant and implementd flows/verified design for many early and mid stage companiesWorked on OVM based methodology and assertions, coverageCloud based tool for HW design using EC2

Sep 2007 - Jun 2010

Verification Consultant

Sunnyvale, California, Us

DDR3 verification/model using denali and verilogEmbedded dram controller verification using random vectorsMethodology for denali/verilog simulation

Jan 2009 - Sep 2009

Verification Consultant

Netlogic Microsystems

Worked on serial interlaken protocol Developed system verilog random methodologyRandom diags and checkers for TX

Sep 2008 - Sep 2009

Verification Consultant

Amd

Santa Clara, California, Us

Developed diags for a gaming chipBring up of the gaming chip in LAB

Aug 2007 - Jul 2008

Design Veriication Lead

Tzero
Oct 2004 - 2005

Design Verification Lead

Velio Communications
2000 - 2005 ~5 yrs

Verification Engineer

Velio
2000 - 2004 ~4 yrs
Team & coworkers

Colleagues at AMD

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3 education records

Ravi Ram education

Ms, Electrical Engineering

San José State University

Bs, Electrical Engineering

Psg College Of Technology

School, High School/Secondary Diplomas And Certificates

Campion Higher Secondary School
FAQ

Frequently asked questions about Ravi Ram

Quick answers generated from the profile data available on this page.

What company does Ravi Ram work for?

Ravi Ram works for AMD.

What is Ravi Ram's role at AMD?

Ravi Ram is listed as AMD Fellow at AMD.

What is Ravi Ram's email address?

AeroLeads has found 1 work email signal at @amd.com for Ravi Ram at AMD.

Where is Ravi Ram based?

Ravi Ram is based in Sunnyvale, California, United States while working with AMD.

What companies has Ravi Ram worked for?

Ravi Ram has worked for Amd, Xilinx, Altera, Bay Design, and Chelsio Communications.

Who are Ravi Ram's colleagues at AMD?

Ravi Ram's colleagues at AMD include Shirely Phua, Pavan Kumar Reddy Ravipally, Kris Socha, Yi-Che Chen, and Rizwan Bhojani.

How can I contact Ravi Ram?

You can use AeroLeads to view verified contact signals for Ravi Ram at AMD, including work email, phone, and LinkedIn data when available.

What schools did Ravi Ram attend?

Ravi Ram holds Ms, Electrical Engineering from San José State University.

What skills is Ravi Ram known for?

Ravi Ram is listed with skills including Systemverilog, Verilog, Functional Verification, Asic, Simulations, Fpga, Embedded Systems, and Soc.

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