Leader for new Initiatives, architecture, planning, deployment and execution of advanced SoC and Firmware development and methodologies at organizational level.Leading new SoC and IP technology for storage solutions based on CXL and HBM.Software/Firmware development for validation of Data Center SSD Product Line.Pre/Post Silicon Validation Management - Test Systems and Embedded Firmware ( SoC ) Planned, evaluated and deployed advanced Emulation and Prototyping techniques and systems for the organization across projects.

Responsible for ASIC SoC Architecture, Design and Development of MICROPLUG Passive Optical Network solution.

Responsible for worldwide emulation (Veloce) customer technical support and success, managing team of 15+ members distributed across the globe. Enabled double digit business growth for emulation business year over year.

Enabled engineering interactions for Tier-1 Strategic Accounts (Sony, Toshiba, and Samsung) and Mobile TV deployment in Hong Kong. Worked with Sales team to secure Tier-1 design wins. • Successfully showcased products at CES in 2006, and 2007, effectively demonstrating their features and benefits to potential clients.• Conducted SWOT analysis and "How to Win" strategies against all competitors in the space.

• Led multiple DSP ASIC SoC generations from 180nm to 90nm into successful production stage that elevated the company to pre-IPO stage with $20M a quarter in revenue.• Delivered 5 generations of productions including 7 production quality demodulator DSP platforms, MPEG-2 decoder and 3 Altera FPGA based head end modulator system.• Enhanced overall engineering development processes to ensure delivery of multiple first pass working production Systems. Incorporated predictable product development and delivery • Served as the primary liaison for vendors (Magma, Altera, and ADI), leading all technical communications and ensuring seamless collaboration for successful product development and integration.• Hands-on, managed all aspects from RTL design, LINT, CDC, constraint generation, timing analysis, DFT and physical design.• Worked with TSMC, SMIC and GSMC to tape out multiple generations of chips successfully.

Worked on design, implementation and validation of first USB IP for Motorola StarTec and Vtec cell phones.