Ravikanth Reddy Email & Phone Number

Us

Us

Santa Clara, Ca, Us

Design Lead for• Ground up Architecture & Design of High Performance Cache Coherent Interconnect Fabric, Directory/SnoopFilter, Home Node and Last Level Cache for CPU and AI/ML Compute• Custom Chiplet IP Protocol Layer for high bandwidth Die-to-Die connectivity for CPU & AI/ML compute• Ground up design of configuration/register network for the entire chip• Design for Debug IP for the entire chip including CPU, AI/ML accelerator & SoC• Help SoC, AI/ML and CPU teams in the areas of SoC Integration, Power & System Management,Memory Management, Firmware & Boot, Physical Design, Verification etc• Program & people management leading cross country teams

Santa Clara, California, Us

• Ground up design of Compute Express Link (CXL) Device side and Host side Transaction Layer, Link Layer and Coherent Fabric interface • System Address Map management, Memory Channel Interleaving, Address normalization and related logic for Server, Client, AI/ML and GPU programs• Interconnect component Soft IP delivery to customers: Accelerator / IO Cache, CXL host & device IP, Coherent Interconnect bridges & gateways

• Architecture and Design of a new L3/LLC Cache subsystem for Exynos ARM CPU• Ground up design of Cache and Coherency subsystem, Prefetchers, Mesh Interconnect• Architecture specification, High speed Low power uArch/RTL Design, Performance evaluation, Timing closure, Floor-plan & Placement guidance etc

Santa Clara, California, Us

• Micro-architecture and RTL design of L2 Cache and Floating Point Unit of Atom CPU Core• Design owner of key Shared Cache modules like CPU Snoop controller, Multi-core interface unit, L2 cache prefetcher, Dynamic L2 cache re-sizing• Floating point instruction set for Secure Hash Algorithm• Design Verification Lead of Floating-Point Unit of Atom CPU core• RTL development, Synthesis, Static timing analysis, Design validation• Development of Architecture Specification document• Architecture and logic design optimizations for high performance and low power, while meeting area targets

Us

• Developed I-PCI, a patented data bus technology that expands PCI Express bus architecture over Ethernet and Internet Networks• Architecture specification, uArch/RTL development and project management• FPGA prototyping for functional and performance evaluation, Linux device driver development

Santa Clara, California, Us

• Worked on efficient RTL modelling for FPGAs and Emulators in the SoC Architecture team • RTL design and FPGA prototyping of various types of Random and Content Addressable Memories, PCI Express IP• Design/Lint rule development for RTL models to synthesize with lesser resources on Veloce Emulator, Xilinx and Altera FPGAs• Developed a configurable Perl application to generate RTL for different kinds of memories

Wilmington, Ma, Us

• RTL design engineer for the ADI SHARC Processor• Design owner of Power Management, Peripheral Interrupt Controller, UART, Timer, PWM, ROM Security, Die to Die Parallel Link Port • Functional verification IP development, Chip top level netlist-to-netlist and RTL-to-netlist equivalence checking, Power estimation using SAIF/PPI for the entire chip, Silicon validation using Linux chip bring-up boards• Extensively programmed in Perl and HTML towards task automation

Mumbai, Maharashtra, In

Worked in the Telecom Switch Simulator tool project. Single person ground up design of a telecom swith simulator & telnet server in C++ in 3 months

Master Of Science, Electrical Engineering

B.Tech, Electrical And Electronics Engineering