Guiding the Design Verification teams across Europe and India to enhance engineering quality and productivity through the integration of AI technologies. Pioneering the architectural design of high-performance chipsets optimized for machine learning inference applications.

Developed a low-power verification environment for Ensemble chipsets, achieving unprecedented power efficiency and rapid wake-up capabilities for optimal performance scalability. The chipset features multiple hardware-controlled dynamic power domains tailored for mission-critical applications. Led the successful tape-out of Balleto devices, catering to the BluetoothLE smart wearable market, with an ultra-low sleep mode current of 700nA, machine learning enhancements, and swift wake-up functionalities

Spearheaded the Design Verification team in developing the first microcontroller tailored for AI edge applications. Successfully Sampled first silicon to customers

SOC integration verification owner for PCIE instances in next gen 5G base station chipset.

Design verification owner for Telemetry Core used in aerospace systems with MRAM, ADC/DAC and several serial protocols

Taped out multiple SOCs with highest quality and track record of bug free designs as individual contributor and verification lead. Worked closely with product marketing, software, architecture and design stakeholders to create verification requirements, provide status, intermediate milestones throughout development cycle. Contributed to variety of roles as team lead on major verification projects for core level and SOC level.