Conceptualized, defined and implemented a highly reconfigurable Spiking Neuron Array Architecture for bio-inspired computation consisting of 4096 multiplexed neurons and over 100k excitatory and inhibitory simultaneous synapses running at 150 MHz on an FPGA using Verilog and Xilinx tools. Key system design parameters such as memory requirements, resource availability, bandwidth, speed, configurability, input/output interface protocols and interaction between the various building blocks were… Show more Conceptualized, defined and implemented a highly reconfigurable Spiking Neuron Array Architecture for bio-inspired computation consisting of 4096 multiplexed neurons and over 100k excitatory and inhibitory simultaneous synapses running at 150 MHz on an FPGA using Verilog and Xilinx tools. Key system design parameters such as memory requirements, resource availability, bandwidth, speed, configurability, input/output interface protocols and interaction between the various building blocks were defined before implementation.Completed design and layout of a novel full custom digital integrate-fire neuron circuit which is significantly area efficient as compared to its analog equivalent. Implemented a configurable and adaptable controller for looking up connection parameters and routing spikes to and from the neuron array. Using circular buffers and block RAMs the system was able to respond to spikes in real time processing 34 million connections per second with a 60 dB dynamic range for weight and synaptic delay. A separate USB time stamping module with a configurable resolution was implemented on the FPGA to monitor and record the activity of the system. Successfully demonstrated the adaptability of various parameters like synaptic weights, delays, threshold, gain etc. to implement different kinds of learning rules (STDP, synchrony etc.) on spiking neural networks. Show less

Designed, guided and co-developed the graduate admissions website for ECE Department at University of Florida using Java and MySQL. Also helped implement various internal websites used by student services / advising at the ECE department.

Worked with the Serial IO and Special Circuits group.Responsibilities included implementing and integrating several key features and state machines for the serial IO blocks (display and pcie) to be part of the next generation Intel processors for ultra books and high end tablets. Worked on the identification, debugging and resolution of clock domain crossing (CDC) violations in the display and pcie IO blocks. As part of the SOC clocking team, helped in defining the clock distribution… Show more Worked with the Serial IO and Special Circuits group.Responsibilities included implementing and integrating several key features and state machines for the serial IO blocks (display and pcie) to be part of the next generation Intel processors for ultra books and high end tablets. Worked on the identification, debugging and resolution of clock domain crossing (CDC) violations in the display and pcie IO blocks. As part of the SOC clocking team, helped in defining the clock distribution architecture for the SOC and the implementation of finite state machines to control and configure Plls in the clock unit. Show less

Teaching Assistant for Electronics Circuits 1 course for ECE Department. Responsibilities included grading homework assignments, mid-term papers, quizzes and teaching a hands on lab for under graduate students.

Developed behavioral models for DES and IDEA algorithms used in cryptography using Verilog. Functionally verified, synthesized and ported the design on FPGA. Comparison of performances of the hardware and software implementations was done.