Raymond Soo Email and Phone Number
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Seasoned test professional across multiple levels of hardware test. Recent experience with medical devices performing verification on neuromonitoring, spine medical devices, electrotherapy, ultrasound and laser treatment systems. Many years of experience with low-level hardware - IC ASIC validation with a telecom wire-line focus. Several years with mid-level hardware on Single Board Computers with multiple I/O features. At each level I have led and contributed to the test planning, scheduling, software scripting, test execution and reporting of products which have entered production. Additional experience with schematic capture PCB design and system level test architecture.Expert or familiar with the following:Test plan writing, scripting, specification writing, electrotherapy, ultrasound therapy, laser therapy, telecom protocol validation, Intel mobile processors (i7, Core2Duo), PPC (68331, 68HC11), T1, E1, DS3, SONET OC-48, ATM, PCIe, GbE, 10 Gigabit Ethernet, USB, DVI, VGA, SATA, FireWire 1394b, NTSC, RS-232, RS-422, I2C, JTAG, VHDL RTL, CPLD, FPGA, Quartus II, OrCAD, Cadence Concept, C, Assembler, Bash, Forth, Expect, Tcl, Open-VPX, VME, XMC, PMC, ATCA, cPCI, backplanes, RTM, oscilloscopes, logic analyzers, protocol analyzers, communication analyzers, function generators, spectrum analyzers, signal generators, first board bringup, debug, Unix, Linux, Windows Embedded, Sharepoint, Agile PLM, SAP, National Instruments TestStand.
Nuvasive (Spine Medical Device)
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- nuvasive.com
- Employees:
- 1
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Senior Verification EngineerNuvasive (Spine Medical Device) May 2014 - PresentSan Diego, Ca, Us• Currently responsible for the verification activities of the electrical and mechanical engineering groups within IOS.• Maintenance and execution of the verification protocols on the NVM5 Neuromonitoring platform. The NVM5 follows the Agile/Scrum development methodology, outputting several new features for every release. Since starting at Nuvasive, I have been a part of 4 successful releases in the last year. The NVM5 platform supports EMG, MEP and SSEP nerve monitoring modalities in support of spine surgery. This verification effort is focused on electrical and human-model interfaces. The latest effort has been to provide input on the next generation verification automation system.• Maintenance and execution of the verification protocols on the Bendini Spine Rod Bending System. The protocols involve the verification of software computed rods used to maintain or correct spine deformities. The system also supports virtual pedical screw mapping using custom IR spatial arrays. Sagittal and coronal spine deformities are captured and inter-operatively calculated for spinal rod implants; verification is performed at every stage. I have been involved in 6 successful releases, (one for 510(k) submission). This verification effort is focused on software and mechanical interfaces.• Execution of the verification protocols on the Guidance 2.0 system. This system involves virtual instrument mapping within a sterile surgical field. Ultra-precision IR sensor technology, spatial arrays, translation fixtures and custom software are combined to create the system. I have been a part of a team performing software and mechanical verification on numerous sub-systems of Guidance 2.0. I have been involved in the initial release of this system; current 510(k) submission is pending. -
Verification Engineer (Contract)Djo Global (Medical Devices) 2012 - 2014Dallas, Tx, Us- Leading the verification effort (small team of 3), on the next generation multi-modality therapy system.- Verification protocol development (from scratch) and execution at the hardware level for electrotherapy waveforms.- Multi-module software verification performed at the system level across E-Stim, Ultrasound, Laser and mixed-mode treatments. Included all black box test protocol writing, execution and reporting.- Preparation of verification reports for FDA 510(k) submission and following ISO 13485 processes.- Troubleshooting at the system level and hardware component levels. Determined root-cause failure for prototype and production level hardware.- Responsible for resource allocation and scheduling of verification effort for multiple concurrent projects.- Re-verification of the Radial Pressure Wave treatment system per IEC 62304 specifications. -
Systems Engineer / Senior Dvt EngineerCurtiss Wright Controls Embedded Computing 2007 - 2012Davidson, North Carolina, Us- System integration and test plan development of a multi-card video capture, compression and transport platform for a UAV environment. Successful demonstrations and acceptance of platforms to customer.- Developed test plans for environmental (MIL-STD-810), EMC (MIL-STD-461, MIL-STD-464) and power (MIL-STD-704).- Debug and workaround resolution on initial release of equipment.- Design Verification Test Lead on Intel based Single Board Computers (SBC) with full I/O complement of PCIe, GbE, SATA, USB, DVI and GPIO. Successfully verified 7 generations of SBCs which transitioned into production.- Tested CoreDuo, Core2Duo and i7 Intel embedded processors over cPCI, VME, VPX and Open-VPX backplane platforms.- Extensive testing of SBCs over several Linux and Windows operating systems. Software scripting experience in Bash shell and Expect.- Environmental testing over temperature and voltage stress conditions. Testing for performance and full operation.- Problem reporting and debug of test failures. Able to review software, configuration scripts, schematics, PCB layouts and datasheets to isolate failure. Comfortable working in lab using oscilloscopes, logic analyzers and other test equipment to pinpoint failures.- Produced requirements compliance test reports for engineering and customer review.- Involved in schematic design and hardware requirements reviews. Tasked to provide input for built-in testability. -
Senior Hardware EngineerContinuous Computing 2005 - 2006San Diego, Ca, Us- Hardware Lead on an Intel Pentium-M based ATCA single board computer.- DVT testing of hardware I/O on single board computers.- Design reviews of schematic designs and PCB layouts.- Successful transition to operations and contract manufacturing.- Successful customer on-site integration and acceptance of initial product. -
Senior Ic Validation Engineer / ManagerVitesse Semiconductor 1998 - 2005- Managed a small group of validation engineers.- Test plan writing and execution of 7+ telecom and switch fabric ASIC products. Functionally tested telecom and datacom protocols including SONET OC-48 (2.488 Gbps), ATM, Packet-over-SONET and CSIX.- Software scripting for individual and concurrent test cases. Software experience with C, Tcl and Assembler. Code written to control CPU accessible registers of device under test. Coded device startup configuration registers and monitored status and error registers.- Developed system and PCB level hardware for IC product validation. Schematic capture using OrCad software. Mentored engineers on PCB design.- Hardware debug of board and IC failures. - Extensive use of oscilloscopes, logic analyzers, communication and jitter analyzers.- Supported FPGA development of an in-house test generator/analyzer. Worked with VHDL RTL, Synplicity, ModelSim and Quartus II. -
Product Validation Engineer LeadPmc-Sierra Semiconductor 1995 - 1998Us- Validation team lead on telecom ASIC devices. Functionally tested telecom protocols at the framer (datacom) and PHY levels. In depth testing of T1, E1, DS3 and ATM technologies.- Test plan development, scheduling and execution for IC devices.- Software scripting for low-level IC functional tests. Software experience with Forth and assembler.- Validation PCB schematic capture design. Used Cadence Concept software tools. Designed motherboards and daughterboards for telecom protocol testing. First pass success on all boards.- Extensive use of oscilloscopes, logic analyzers, waveform generators, communication and jitter analyzers. -
Hardware TechnologistMpr Teltech 1990 - 1995- Hardware support for optical fiber based video conferencing system.- Network planning and resource allocation for new customer sites.- Manufacturing support and training on initial and full production builds.- Troubleshooting and repairs on all proprietary hardware.
Raymond Soo Skills
Raymond Soo Education Details
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British Columbia Institute Of TechnologyElectrical And Electronics Engineering
Frequently Asked Questions about Raymond Soo
What company does Raymond Soo work for?
Raymond Soo works for Nuvasive (Spine Medical Device)
What is Raymond Soo's role at the current company?
Raymond Soo's current role is Senior Verification Engineer (Contract) at Nuvasive.
What is Raymond Soo's email address?
Raymond Soo's email address is rs****@****hoo.com
What schools did Raymond Soo attend?
Raymond Soo attended British Columbia Institute Of Technology.
What skills is Raymond Soo known for?
Raymond Soo has skills like Debugging, Pcb Design, Hardware Architecture, Hardware, Testing, Fpga, Pcie, Systems Engineering, Processors, Usb, I2c, Embedded Systems.
Who are Raymond Soo's colleagues?
Raymond Soo's colleagues are Caryn Stedillie, Michelle Cruz, Stephanie Sheehan, Joanna Di Silvio, Gabby Messerschmitt, Isabelle Latsch, Madisyn Baxter, Cnim.
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