Ray Vargas personal email
- Valid
Diverse background with 30+ years in full product development cycle of microprocessors, SoC platforms, and mixed-signal ASICs for audio/video digital signal processing applications. Extensive experience in all aspects of VLSI design and SoC design methodology -- from microarchitecture to algorithm development to RTL and physical design including custom datapath, standard cell place/route, FPGA. Proficient in all aspects of verification -- functional, physical, formal, mixed-signal. Consistently achieved production-worthy first silicon. Deployed methodology and testbench environments to maximize productivity, incorporating best practices in design-for-reuse/verification/debug/test. Effective multidisciplinary team-builder and mentor.EXPERTISE•High speed logic design, computer arithmetic algorithms, floating-point datapaths•Digital signal/image processing, video compression•SoC, ASIC, DSP, CPU design•Synthesis, STA, and low-power design•Project database setup and design methodology flow•Behavioral modeling of mixed-signal analog circuits in SystemVerilogTOOLS•Verilog/VHDL, SystemVerilog, SVA, NCsim, VCS, ModelSim, Verdi, Spyglass lint, Questa CDC•DesignWare, DesignCompiler, Encounter RC, LEC (Conformal, Formality), PrimeTime, CTGen•Xilinx ISE, Vivado, CoreGen; SynplifyPro; Synopsys HAPS•C/C++, assembly, shell scripting, Make, Perl, Python, Tcl, Matlab, XML•MS Project + Office, git, SVN, Perforce, JIRA
Rapid Pixel, Llc
-
Owner And ConsultantRapid Pixel, LlcAustin, Tx, Us
-
Owner/ConsultantRapid Pixel, Llc 2005 - PresentIndependent consulting and contracting services: - VLSI/SoC/ASIC/FPGA design and implementation - audio/video signal processing, data compression, sample rate conversion - integer and floating-point ALU design and pipelined datapath design - asynchronous interfaces and clock domain synchronization - static timing analysis and critical path redesign; logic synthesis and clock tree synthesis - design methodology, including revision control and configuration management - low power designExpert witness:- Independent patent review and assessment
-
Contractor - Digital Design And Chip IntegrationAmd Nov 2017 - Nov 2019Santa Clara, California, Us• Automated and optimized compile of IEEE 802.11ad WiGig baseband/MAC subsystem for wireless video codec SoC onto Synopsys HAPS emulation platform.• Debugged Matlab algorithm models for IEEE 802.11ad WiGig baseband processing.• Assisted in design and timing closure of proprietary low-latency video codec w/ DisplayPort interface.• Physical design verification including CDC/lint checks, LEC, LVS, static timing closure, and dynamic power analysis. Improved scripted flows for design methodology and config management releases. -
Contractor - Mixed-Signal ModelingRenesas Electronics Jul 2017 - Dec 2017Koto-Ku, Toyosu, Tokyo, Jp• Authored reference model for PPM voltage controller used in constrained-random testbench. Debugged and redesigned RTL to operate within VR14 specs. -
Contractor - Mixed-Signal ModelingCirrus Logic Nov 2015 - Jun 2017Austin, Tx, Us• Designed and verified a MASH architecture ADC.• Supported system-level model build with RTL, gate-level netlists, analog behavioral models and schematics to simulate in UVM, AMS, manufacturing test and FPGA emulation environments. -
Verification SpecialistCorrect Designs Mar 2015 - Jul 2015Austin, Tx, Us• Authored constrained random testbench and SVN assertions to verify design of reactive brownout controller for an audio codec. Added directed tests to improve overall code coverage of codec. -
Independent ContractorIntersil Corporation Jul 2014 - Jan 2015Koto-Ku, Toyosu, Tokyo, Jp• Integrated 3rd party IP for asynchronous non-volatile RAM cell into synchronous design for digital power management ASIC. -
Independent ContractorCirrus Logic Feb 2014 - Jul 2014Austin, Tx, Us• Redesigned predictive brownout controller for audio amp to reduce area/routing congestion and eliminate timing critical paths. Mentored employee designer in datapath design.
-
Contractor - Digital Design And IntegrationIntersil Corporation Mar 2013 - Feb 2014Koto-Ku, Toyosu, Tokyo, Jp• Coded SystemVerilog behavioral models for analog mixed-signal portion of digital multi-phase PWM controller for VR13-compliant digital power management ASIC. Auto-generated symbol library for schematics using Cadence verilogIn.• Optimized control loop datapaths to improve critical path timing.
-
Digital Design ConsultantInview Technology Corporation May 2012 - Mar 2013• Architected, designed, and optimized FPGA RTL to implement algorithms for compressive sensing IR camera. Fully automated the design methodology for Xilinx FPGA builds using Make.
-
Subcontractor - Chip IntegratorCirrus Logic Jul 2011 - Dec 2011Austin, Tx, Us• Designed, verified, implemented, and taped-out an HDA audio codec derivative in 2 months. Added new parametric EQ filter and PC-beep functions. First silicon released to volume production.• Generated timing constraints, verified timing closure and LEC. Inserted DFT scan and generated scan testvectors (TetraMax) used for manufacturing test.
-
Contractor - Digital DesignerD2Audio Jun 2009 - Sep 2010UsDebugged interface timing issues on audio codec / touch-screen controller mixed-signal ASIC. Drove design methodology for FPGA emulation/validation, equivalence checking, and clock tree synthesis. -
Contractor -Digital Design And Fpga ImplementationAvnera Corporation 2007 - 2009Beaverton, Or, Us• Developed High Definition Audio (HDA) bridge interface FPGA to communicate with standard I2S audio codecs. Designed and verified RTL, specified prototype PCB board, generated FPGA bitfile, and successfully demonstrated working PCB prototype. -
Contractor - Digital Design And Ic ImplementationSigmatel 2002 - 2008• Specified design of 5-FPGA PCB system for emulating a Personal Media Player SoC. Partitioned and compiled RTL design of SoC across 5 FPGAs, generated bitfiles (Xilinx, Synplicity, Certify), and performed initial board bringup. Enabled fast prototyping for validation of AMBA-based video and graphics subsystems.• Created build environment for repeatable gate-level simulations of SDF-annotated full-chip netlist for MP3 SoC. Instituted revision control tagging to retrieve design database consistent with each netlist.• Automated generation of Verilog/C/Perl header files used in design RTL and verification testcases directly from specification document of programmer-visible register set. Reduced design iteration turn-around time to minutes for related ECO’s.• Designed SPDIF, ADAT, and I2S interfaces for AC97/HD-audio codec. Restructured on-chip interfaces to reuse common FIFO controller to decrease time-to-market for derivative products.• Led digital design of 2 derivative HD-audio codecs, from RTL edits to synthesis/scan-insertion to timing closure.
-
Senior Member Of Technical StaffEquator Technologies 1997 - 2002• Developed SRT radix-8 division algorithm and RTL-to-layout implementation for a 0.3um semi-custom 200MHz arithmetic unit for integer divide/remainder and floating-point divide/reciprocal/sqrt operations on the MAP1000 VLIW broadband signal processor for video and image processing. Led physical design through synthesis, timing analysis, and place & route.• Implemented 300MHz texture filter and blending unit for 3D graphics pipeline.• Proposed and implemented SoC methodology improvements encompassing design-for-reuse/verification/debug/test best practices.
-
Senior Digital DesignerCrystal Products Division Of Cirrus Logic 1993 - 1997Austin, Tx, Us• Lead engineer supervising 3-man team on design, verification and in-circuit emulation of MPEG-2 video decoder. Led functional integration of MPEG-2 IP core. Architected and designed display postprocessor with OSD graphics overlay. Designed interpolation filter to pan, resize, and reformat decoded MPEG picture for CCIR-656 NTSC/PAL output.• Lead digital engineer on various codecs. Designed RAM-based FIFO and asynchronous parallel-port interface for 16-bit dual channel data/fax/modem. Designed ISA-bus PlugNPlay controller.
-
Senior Electrical EngineerMotorola Semiconductor 1989 - 1993Austin, Texas, UsCustom circuit design, floorplanning and physical verification of 0.8um 66-MHz, 3-stage 80-bit IEEE-754 Floating-Point Adder for 88110 SuperScalar RISC microprocessor. Awarded 2 patents. -
Associate Electrical EngineerIbm 1987 - 1989Armonk, New York, Ny, UsRTL design of System/390 Floating-Point Add/Divide chip for midrange processor.
Ray Vargas Skills
Ray Vargas Education Details
-
University Of California, BerkeleyElectrical Engineering -
University Of MichiganElectrical Engineering
Frequently Asked Questions about Ray Vargas
What company does Ray Vargas work for?
Ray Vargas works for Rapid Pixel, Llc
What is Ray Vargas's role at the current company?
Ray Vargas's current role is Owner and Consultant.
What is Ray Vargas's email address?
Ray Vargas's email address is va****@****ail.com
What schools did Ray Vargas attend?
Ray Vargas attended University Of California, Berkeley, University Of Michigan.
What are some of Ray Vargas's interests?
Ray Vargas has interest in Computer Arithmetic, Small/micro Business Development.
What skills is Ray Vargas known for?
Ray Vargas has skills like Integrated Circuit Design, Digital Ic Design, High Speed Digital Design, Vlsi, Semiconductors, Asic, Soc, Fpga, Fpga Emulation, Digital Signal Processors, Microprocessors, Rtl Design.
Free Chrome Extension
Find emails, phones & company data instantly
Aero Online
Your AI prospecting assistant
Select data to include:
0 records × $0.02 per record
Download 750 million emails and 100 million phone numbers
Access emails and phone numbers of over 750 million business users. Instantly download verified profiles using 20+ filters, including location, job title, company, function, and industry.
Start your free trial