Ray Vargas Email & Phone Number

Austin, Tx, Us

Independent consulting and contracting services: - VLSI/SoC/ASIC/FPGA design and implementation - audio/video signal processing, data compression, sample rate conversion - integer and floating-point ALU design and pipelined datapath design - asynchronous interfaces and clock domain synchronization - static timing analysis and critical path redesign; logic synthesis and clock tree synthesis - design methodology, including revision control and configuration management - low power designExpert witness:- Independent patent review and assessment

Santa Clara, California, Us

• Automated and optimized compile of IEEE 802.11ad WiGig baseband/MAC subsystem for wireless video codec SoC onto Synopsys HAPS emulation platform.• Debugged Matlab algorithm models for IEEE 802.11ad WiGig baseband processing.• Assisted in design and timing closure of proprietary low-latency video codec w/ DisplayPort interface.• Physical design verification including CDC/lint checks, LEC, LVS, static timing closure, and dynamic power analysis. Improved scripted flows for design methodology and config management releases.

Koto-Ku, Toyosu, Tokyo, Jp

• Authored reference model for PPM voltage controller used in constrained-random testbench. Debugged and redesigned RTL to operate within VR14 specs.

Austin, Tx, Us

• Designed and verified a MASH architecture ADC.• Supported system-level model build with RTL, gate-level netlists, analog behavioral models and schematics to simulate in UVM, AMS, manufacturing test and FPGA emulation environments.

Austin, Tx, Us

• Authored constrained random testbench and SVN assertions to verify design of reactive brownout controller for an audio codec. Added directed tests to improve overall code coverage of codec.

Koto-Ku, Toyosu, Tokyo, Jp

• Integrated 3rd party IP for asynchronous non-volatile RAM cell into synchronous design for digital power management ASIC.

Austin, Tx, Us

• Redesigned predictive brownout controller for audio amp to reduce area/routing congestion and eliminate timing critical paths. Mentored employee designer in datapath design.

Koto-Ku, Toyosu, Tokyo, Jp

• Coded SystemVerilog behavioral models for analog mixed-signal portion of digital multi-phase PWM controller for VR13-compliant digital power management ASIC. Auto-generated symbol library for schematics using Cadence verilogIn.• Optimized control loop datapaths to improve critical path timing.

• Architected, designed, and optimized FPGA RTL to implement algorithms for compressive sensing IR camera. Fully automated the design methodology for Xilinx FPGA builds using Make.

Austin, Tx, Us

• Designed, verified, implemented, and taped-out an HDA audio codec derivative in 2 months. Added new parametric EQ filter and PC-beep functions. First silicon released to volume production.• Generated timing constraints, verified timing closure and LEC. Inserted DFT scan and generated scan testvectors (TetraMax) used for manufacturing test.

Us

Debugged interface timing issues on audio codec / touch-screen controller mixed-signal ASIC. Drove design methodology for FPGA emulation/validation, equivalence checking, and clock tree synthesis.

Beaverton, Or, Us

• Developed High Definition Audio (HDA) bridge interface FPGA to communicate with standard I2S audio codecs. Designed and verified RTL, specified prototype PCB board, generated FPGA bitfile, and successfully demonstrated working PCB prototype.

• Specified design of 5-FPGA PCB system for emulating a Personal Media Player SoC. Partitioned and compiled RTL design of SoC across 5 FPGAs, generated bitfiles (Xilinx, Synplicity, Certify), and performed initial board bringup. Enabled fast prototyping for validation of AMBA-based video and graphics subsystems.• Created build environment for repeatable gate-level simulations of SDF-annotated full-chip netlist for MP3 SoC. Instituted revision control tagging to retrieve design database consistent with each netlist.• Automated generation of Verilog/C/Perl header files used in design RTL and verification testcases directly from specification document of programmer-visible register set. Reduced design iteration turn-around time to minutes for related ECO’s.• Designed SPDIF, ADAT, and I2S interfaces for AC97/HD-audio codec. Restructured on-chip interfaces to reuse common FIFO controller to decrease time-to-market for derivative products.• Led digital design of 2 derivative HD-audio codecs, from RTL edits to synthesis/scan-insertion to timing closure.

• Developed SRT radix-8 division algorithm and RTL-to-layout implementation for a 0.3um semi-custom 200MHz arithmetic unit for integer divide/remainder and floating-point divide/reciprocal/sqrt operations on the MAP1000 VLIW broadband signal processor for video and image processing. Led physical design through synthesis, timing analysis, and place & route.• Implemented 300MHz texture filter and blending unit for 3D graphics pipeline.• Proposed and implemented SoC methodology improvements encompassing design-for-reuse/verification/debug/test best practices.

Austin, Tx, Us

• Lead engineer supervising 3-man team on design, verification and in-circuit emulation of MPEG-2 video decoder. Led functional integration of MPEG-2 IP core. Architected and designed display postprocessor with OSD graphics overlay. Designed interpolation filter to pan, resize, and reformat decoded MPEG picture for CCIR-656 NTSC/PAL output.• Lead digital engineer on various codecs. Designed RAM-based FIFO and asynchronous parallel-port interface for 16-bit dual channel data/fax/modem. Designed ISA-bus PlugNPlay controller.

Austin, Texas, Us

Custom circuit design, floorplanning and physical verification of 0.8um 66-MHz, 3-stage 80-bit IEEE-754 Floating-Point Adder for 88110 SuperScalar RISC microprocessor. Awarded 2 patents.

Armonk, New York, Ny, Us

RTL design of System/390 Floating-Point Add/Divide chip for midrange processor.

Mse, Electrical Engineering

Bse, Electrical Engineering