Working in Implementation activities on multimillion gate SoC's for Artificial Intelligence, machine learning, Internet of things in deep sub micron technologies(5nm, 7nm, 10nm, 14nm, 16nm, 28nm, 40nm, Intel 11 and Intel 14 process).Expertise in:-> Floor planning-> Power planning-> Placement-> Clock Tree Synthesis and Optimization-> Routing-> Delay and Glitch Cross Talk Analysis-> Multi-Corner Optimization-> Efficient ECO implementation-> Static Timing Analysis-> Physical verification-> Strong CMOS concepts-> Function ECO's Implementation Tools: IC Compiler, Innovus, IC Compiler2, Fusion Compiler, Prime Time, First Encounter, Calibre, Redhawk, Primetime, Tweaker, VCLP, Formality, STAR-RC