Design and Architect of Analog and Mixed signal circuits including, Audio Codec, Energy Harvesting Circuits, Photonics RF Integer/Fractional N PLL/frequency synthesizers, CT and DT Sigma Delta ADCs, Sigma Delta DAC, SAR ADCs, LDO, amplifiers.Analysis of security systems.

Research, design and consulting on precision measurements.

Develop innovative new custom ASIC/IC based designs for enhancing performance and solving a broad range of issues, Architect, design and verify Analog/Mixed signal IC circuits, systems, algorithms, Determine custom IC design flow, technology node, PDK and procedure of verificationProjects and Circuit Modules experienced for system level and transistor IC design for over $30 Million products, RF Switches, ultra low noise Oscillator,Front end circuit of 1GHz 14Bits 100V Oscilloscope, Milliohms resolution Time-Domain Reflectometry (TDR) circuit, TDC, DLL, Wideband amplifier, Gm-C Analog filter with RC tuning, SAR ADC, DAC, MDAC, Sampling Hold, Pulse Generator, High voltage amplifiers, DIO, Bus driverPackage experience, QFN, TQFP, BGA on different foundries and IC packaging servicesLead lab engineers in taking lab measurements to validate IPs. Support ECAD tools and operating system (linux)Work with and support marketing to define and develop new products included system production

Designing circuits and systems for the front end of the Oscilloscope of High Speed and High resolution data acquisition cards and digitizing instrumentsSupervising Integrated Circuit Production Procedure and verificationDesigning the First high precision NI’s Custom Integrated CircuitPerforming of Circuit and system design tools evaluation Experience of Analog Custom IC design tools: Mentor, Tanner, Silvaco, Synopsys, AWR, Cadence Presenting a number of NI’s technical conferences in Radio frequency (RF) Systems, Optical Communications, high speed and high Precision Circuits and System DesignDesigning Passive and Active Analog Filter Synthesis Tool using LabVIEW scripting.

Senior Engineer and Design Manager in a team to design microprocessors. I had a chance to use 45-90nm CMOS SOI technologies to design DDR2/DDR3 and Hyper Transport technology (HT) link. I derived I/O development ranging from feasibility to production.