• Primarily worked on developing a compiler back-end for the P4 language that targeted FPGA enabled SmartNICs.• Produced full compiler-to-40G NIC designs which were demoed at multiple conferences and workshops including Mobile World Congress, SIGCOMM, and the early P4.org events.• In collaboration with Barefoot Networks built an Inband Network Telemetry demo using multiple SmartNICs connected to a Tofino switch with live data streamed to their DeepInsight analytics software.

My research focused on how hardware accelerators (FPGAs & GPUs) could be used to improve performance for Database, and High Performance Computing (HPC) applications.• Advised by Dr. Walid Najjar.• I built a C to VHDL compiler for irregular applications called CHAT. It uses parts of the SUIF, and LLVM compilers.• Looked at ways to build multi-threaded FPGA designs on current FPGA platforms like the Convey HC machines, and Pico Platforms.• Looked at how GPUs could be used for XML Path Filtering• Looked at how In-Memory Hash Joins could be done on FPGAs where memory latency is in the order of hundreds of cycles.

Computer Architecture: Labs had students build working CPUs in VHDL, implement caches & content addressable memory (CAM).Compilers: Labs focused on building a complete compiler for a mini-C language. Labs taught students how to use Flex, and Bison. Intro to C++: Taught CS & Non-CS majors how to program in C++

Worked with the Digital Communications IC group. Looked into ways for improving the performance of relational join on large datasets using FPGAs to reduce the workload in software.

• Worked with the System Z group. • Designed and implemented a relational hash-join component in VHDL• The component could be integrated into an existing FPGA framework for accelerating database analytics operations.• Results were published in a paper at FCCM 2013

• Worked on the Riverside Optimizing Compiler for Configurable Computing (ROCCC)• Extended support to Floating-point operations, by integrating IP cores from Xilinx• Developed a port for a PLB bus so the compiled kernels could be placed into EDK designs with a MicroBlaze/PicoBlaze processor