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Summary• iPad Systems EE - 7 iPads: Mini 2-5, iPad 5-7th generation, in addition to numerous unreleased programs• 9 major product platforms - from concept to production• 6 startup environments on 9 major product platforms - from concept to production• 6 years of management experience, including Director/Senior Manager title• Successful at hiring, motivating and retaining employees• Proven track record for delivering projects on time• Master’s degree from MITExperience: • Consumer product and networking equipment design• High-speed rigid PCB and flex design, development hardware• Design and test for signal integrity, coexistence, desense, ESD• FPGAs, CPLDs, VHDL• Cadence Concept-HDL and Allegro• “Student” of Python and Matlab• Serial interfaces, sensors, displays, capacitive touch, cameras, audio, Lithium-Ion batteries• Lab equipment, including high-speed oscilloscopes, EIS battery tester, logic analyzers• Experience with mechanical/chassis design, including airflow and thermal issues.• Regulatory work including EMI debug and NEBS testing.• China factory visits: prototype to production, statistical analysis• Successful track record for “first-time” working boards.• Good writing and communication skills.
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Hardware EngineerApple Feb 2013 - PresentCupertino, California, UsiPad Hardware Engineering -
Hardware Engineering DirectorStoke, Inc. Oct 2009 - Feb 2013Richardson, Texas, Us• Led a team of hardware engineers to delivery a state-of-the-art 2 x 10Gbps line card on time and within budget.• Contributed in both managerial and technical roles across of a number of projects and departments. -
Senior Technical Lead - HardwareRohati Systems Jul 2007 - Oct 2009Sunyvale, Ca, Us• Designer for an ATCA-sized 22-layer linecard. Major subsystems include multi-core MIPS processors, 10GbE XFP interfaces, serdes backplane, multiple high-speed buses and memory interfaces.• Lead engineer for all thermal aspects of chassis and board design. Selected and interacted with an outside thermal consulting firm to model boards. Helped specify heatsinks for all critical components. Ran thermal tests to characterize and validate thermal performance.• Lead engineer for all design elements pertaining to EMC and safety compliance. Specified system grounding scheme and worked with all engineers to ensure consistent design practices. Specified metallic port protection devices and spread-spectrum clock generation. Efforts led to final certification of to all global EMC requirements with virtually no changes to hardware.• Liaison to chassis vendor and all mechanical/cosmetic design changes. Requested and tracked all ECOs. Designed lighting technique for chassis logo. -
Manager, HardwareStoke, Inc. Jun 2004 - Jul 2007Richardson, Texas, Us• Evaluated switching technologies for backplane switch fabrics.• Worked with a local outsource design firm during schematic capture and layout.• Defined the chassis/board grounding and bonding strategy to satisfy EMC and telecom requirements.• Manager and technical lead on the 14-slot chassis – a platform capable of dissipating 5000W in 1/3 of a telco rack while meeting NEBS environmental criteria.• Actively participant in Quality of Service discussions, requirements and documentation.• Lead a working group tasked with architecting a Deep Packet Inspection subsystem comprised of a multi-core processor and regular expression coprocessor. • Designed main board CPLDs in VHDL.• Actively involved with matters relating to signal integrity, thermal issues, homologation, safety (creepage and clearance), mechanical design and airflow, industrial design, I2C bus, hardware architecture futures, PLM/Operation, RoHS compliance and product sustaining. -
Member Technical StaffFoundry Networks Dec 2003 - Jun 2004Us• Co-designer of the “IronFist” ServerIronGT 1RU platform board. -
Hardware Technical LeadTahoe Networks, Inc. Jan 2001 - Oct 2003• Evaluated switch-fabric chipsets and serdes components from multiple vendors. Selected vendor based on technical merits and strategic business relationship issues after extensive three-month investigation.• Responsible for “SWC” switch-fabric card, from concept to production. Prototypes brought up in ~24hrs.• Responsible for system-wide datapath traffic engineering, including queuing, scheduling/shaping, and flow-control mechanisms.• Developed novel method for implementing a traffic-management chipset for improved performance.• Discovered acritical bug and recommended a specific corrective action for a vendor’s ASSP, triggering a chip re-spin.• Created a 20G fabric architecture using an AMCC/MMC chipset in a manner not originally intended by MMC.• Benchmarked Xilinx Virtex2Pro RocketIO interoperability with Mindspeed serdes.• Other projects include SDRAM timing analysis, EMI debug, GigE SFP interface, Powerpoint slide preparation for customer/partner presentations.
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Senior EngineerShasta Networks Mar 1998 - Jan 2001• Responsible for the “SFC” switch-fabric card, from concept to production.• Responsible for the “HLC” HSSI line card, from concept to production.• Coordinated NEBS Level III testing and product changes and achieved full compliance.• Evaluated mechanical design firms and assisted chassis design as technical liaison.• Managed a group of three engineers.• Participated in “next-generation” BRAS architecture work, focusing on a higher capacity switching fabric and backplane.• Assisted with heatsink selection and testing, as well as EMI debug.
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Hardware ManagerNortel Networks Mar 1998 - Jan 2001CaFrom acquisition of Shasta Networks -
Senior Member Of Technical StaffZeitnet Jun 1995 - Mar 1998• Project Lead - 6A000 Module - Responsible for all project-related activities, including the work supervision of 4+ employees. Project involved major electrical and mechanical modifications to the ZeitNet 2.5G ATM switch to create a hot-swappable module for the Cabletron SmartSwitch 6000 chassis. • Quad I/O Module - Designed two versions of a four-port interface board for an ATM switch, with a total throughput of 622 Mbps. Prototype version included the design of an ATM MultiPHY UTOPIA interface controller. Other assignments included backplane design and WAN ATM adapter projects.• Cell Storage Module - Designed an 11” x 16” board which implements the shared-memory output-queued cell storage function for a “next generation” ATM switch. • Chassis Design - Championed the chassis development. Technical liaison to an outside mechanical contracting firm. Designed the card ejector.
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Senior EngineerEnterasys Networks Jun 1995 - Mar 1998San Jose, Ca, UsFrom acquisition of ZeitNet, Inc. -
Senior EngineerNetwork Equipment Technologies & Adaptive, Inc. Apr 1990 - Jun 1995• ATM Circuit Emulation - Defined system hardware requirements for support of constant bit-rate services. Contributed to evolving standards documents at the ATM Forum.• Designed the Multiport Data Module, Peripheral Function Module, Peripheral Shelf and Octal DS1 Port Module
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Senior EngineerIbm & Rolm Systems, Inc. May 1988 - Apr 1990• Miscellaneous projects within the Hardware Sustaining group
Rob Hastings Skills
Rob Hastings Education Details
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Massachusetts Institute Of TechnologyElectrical Engineering -
Case Western Reserve UniversityElectrical Engineering
Frequently Asked Questions about Rob Hastings
What company does Rob Hastings work for?
Rob Hastings works for Apple
What is Rob Hastings's role at the current company?
Rob Hastings's current role is iPad Hardware Engineering.
What is Rob Hastings's email address?
Rob Hastings's email address is robhastings@me.com
What schools did Rob Hastings attend?
Rob Hastings attended Massachusetts Institute Of Technology, Case Western Reserve University.
What are some of Rob Hastings's interests?
Rob Hastings has interest in Aviation, Finance And Investing, Home Theater And Movies, Fitness, Wine.
What skills is Rob Hastings known for?
Rob Hastings has skills like Switches, Hardware, Debugging, Team Management, Team Leadership, Architecture.
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