Richard Ho Email & Phone Number

San Francisco, California, United States

Mountain View, California, United States

Mountain View, California, United States

Leading silicon engineering - including digital architecture and design, functional verification, physical design, analog and silicon photonics.

Sunnyvale

Providing silicon solutions to Google's Infrastructure and Cloud. - TPU (Tensor Processing Unit) - ML inference and training workloads for internal Google products and external Cloud customers through CloudTPU - VCU (Video Coding Unit) - YouTube (and Stadia) video transcoding accelerator - EdgeTPU - developed the foundation of the ML-acceleration inside the Pixel Tensor chip - IPU (Infrastructure Processing Unit)Cross-functional leadership of Google TPU… Show more Providing silicon solutions to Google's Infrastructure and Cloud. - TPU (Tensor Processing Unit) - ML inference and training workloads for internal Google products and external Cloud customers through CloudTPU - VCU (Video Coding Unit) - YouTube (and Stadia) video transcoding accelerator - EdgeTPU - developed the foundation of the ML-acceleration inside the Pixel Tensor chip - IPU (Infrastructure Processing Unit)Cross-functional leadership of Google TPU projects. - Led the delivery of inference and training TPU chips across multiple generations. - Drove the methodology and chip-design infrastructure that delivered A0 success on multiple TPU projects on aggressive schedules.Direct functional leadership of: - Functional Design Verification across multiple Google silicon projects includingTPU, VCU and IPU. - Built and grew the team, scaled the technical leadership, helped many star contributors. - Formal Property Verification team across projects - Build and grew the team, developed the methodology to complement DV. - Application of ML techniques to accelerate chip design in implementation and verification. - Initiated the use of ML for chip-design, resulting in cross-organizational and cross-functional collaboration that produced tools used in production design of TPU, published in Nature.Check press about Google's chip activities for a hint about some of the problems we're working on. Show less

High quality open source hardware IP, systems and tools.

Stanford

Providing some teaching support for Design Verification to EE 271 - Introduction to VLSI Design

Sunnyvale, Ca

Calxeda was a pioneering company that used low power ARM cores integrated with high speed communications to provide high efficiency servers for storage and compute nodes in data centers.At Calxeda, I built a team from the ground up to verify a next generation hyper-scale communication fabric for data centers. Starting from a high level architecture, developed a comprehensive verification strategy based on System Verilog simulation test environments using UVM and static techniques. Staffed… Show more Calxeda was a pioneering company that used low power ARM cores integrated with high speed communications to provide high efficiency servers for storage and compute nodes in data centers.At Calxeda, I built a team from the ground up to verify a next generation hyper-scale communication fabric for data centers. Starting from a high level architecture, developed a comprehensive verification strategy based on System Verilog simulation test environments using UVM and static techniques. Staffed the team and guided implementation of verification environments. Performed test bench implementation and test writing. Developed assertion methodology and wrote assertions. Implemented design verification infrastructure for lint checking, static analysis and regressions. Show less

Cupertino, Ca

D. E. Shaw Research builds super-computer class multi-node machines to perform molecular dynamics simulation of biological systems. The Anton 1 and Anton 2 machines that I helped build have pushed the frontiers of protein folding simulation and the research that is enabled by highly accurate, long timescale molecular dynamics simulation. Both machines won the Gordon Bell Prize awarded by the ACM.My role included hands-on verification, evaluation of new technologies, managing adoption of… Show more D. E. Shaw Research builds super-computer class multi-node machines to perform molecular dynamics simulation of biological systems. The Anton 1 and Anton 2 machines that I helped build have pushed the frontiers of protein folding simulation and the research that is enabled by highly accurate, long timescale molecular dynamics simulation. Both machines won the Gordon Bell Prize awarded by the ACM.My role included hands-on verification, evaluation of new technologies, managing adoption of tools and continual evaluation of the methods deployed to ensure efficient, effective verification.• Planned, managed and executed formal verification of large ASIC with multiple processor cores and high-speed, low-latency communication network.• Co-developed a new method of using formal verification that highlights parts of a design that are inherently difficult to verify. The technique is able to identify these problem areas in the register-transfer level (RTL) description early, so that the engineering team can make changes to speed up verification closure. The technique uses a novel evaluation method based on inconclusive formal verification results.• Developed a method of using formal verification with waypoints to track down the root cause of post-silicon defects that could not be reproduced in simulation and are beyond the reach of standard formal verification methods.• Developed and deployed a method and tools to simulate the effects of metastability in asynchronous clock- domain crossings.• Co-developed and deployed a method and tools to check for the effects of X-pessimism and X-optimism that could lead to differences between RTL and gate-level simulation. Show less

Chaired the multi-company committee that developed and published the Accellera Unified Coverage Interoperability Standard (UCIS) V1.0. Worked with both tool developers and design engineers from Intel, Freescale, IBM, ARM, Xilinx, AMD, Oracle (Sun), Synopsys, Cadence, Mentor Graphics, Jasper Design Automation and many others to craft an industry-wide standard for verification coverage unification.

San Jose, Ca

Manager of a team of Application Engineers who worked closely with leading ASIC and SoC design teams (including Sun, AMD, Intel, HP, Cisco, Nortel) to maximize the benefit from using assertions, coverage points and formal verification within simulation-based verification methodologies.

San Jose, Ca

A co-founder of 0-In Design Automation, which was a pioneer of the use of assertions libraries for verification of RTL designs. This developed into the assertion-based verification (ABV) methodology now commonly used for functional verification of ASICs, SoCs and processors. While at 0-In, also pioneered the combination of formal verification techniques with simulation (known as semi-formal, dynamic formal or hybrid formal) to provide more thorough analysis of large and complex digital designs.… Show more A co-founder of 0-In Design Automation, which was a pioneer of the use of assertions libraries for verification of RTL designs. This developed into the assertion-based verification (ABV) methodology now commonly used for functional verification of ASICs, SoCs and processors. While at 0-In, also pioneered the combination of formal verification techniques with simulation (known as semi-formal, dynamic formal or hybrid formal) to provide more thorough analysis of large and complex digital designs. At 0-In, worked as an engineer, a technical lead and an engineering manager to productize and bring to market products based on these techniques. Later, was in charge of marketing activities including both outbound and inbound technical and product marketing. Mentor Graphics acquired 0-In in Sept 2004. Show less

Ph.D, Computer Science

Technical Management Program

M.Eng, B.Sc (Hons), Microelectronic Systems Engineering