Richard Ho Email & Phone Number

San Francisco, California, United States

Mountain View, California, United States

Mountain View, California, United States

Leading silicon engineering - including digital architecture and design, functional verification, physical design, analog and silicon photonics.

Sunnyvale

Providing silicon solutions to Google's Infrastructure and Cloud. - TPU (Tensor Processing Unit) - ML inference and training workloads for internal Google products and external Cloud customers through CloudTPU - VCU (Video Coding Unit) - YouTube (and Stadia) video transcoding accelerator - EdgeTPU - developed the foundation of the ML-acceleration inside.

High quality open source hardware IP, systems and tools.

Stanford

Providing some teaching support for Design Verification to EE 271 - Introduction to VLSI Design

Sunnyvale, CA

Calxeda was a pioneering company that used low power ARM cores integrated with high speed communications to provide high efficiency servers for storage and compute nodes in data centers.At Calxeda, I built a team from the ground up to verify a next generation hyper-scale communication fabric for data centers. Starting from a high level architecture.

Cupertino, CA

• D. E. Shaw Research builds super-computer class multi-node machines to perform molecular dynamics simulation of biological systems. The Anton 1 and Anton 2 machines that I helped build have pushed the frontiers of.
• Planned, managed and executed formal verification of large ASIC with multiple processor cores and high-speed, low-latency communication network.
• Co-developed a new method of using formal verification that highlights parts of a design that are inherently difficult to verify. The technique is able to identify these problem areas in the register-transfer level.
• Developed a method of using formal verification with waypoints to track down the root cause of post-silicon defects that could not be reproduced in simulation and are beyond the reach of standard formal verification.
• Developed and deployed a method and tools to simulate the effects of metastability in asynchronous clock- domain crossings.
• Co-developed and deployed a method and tools to check for the effects of X-pessimism and X-optimism that could lead to differences between RTL and gate-level simulation. Show less

Chaired the multi-company committee that developed and published the Accellera Unified Coverage Interoperability Standard (UCIS) V1.0. Worked with both tool developers and design engineers from Intel, Freescale, IBM, ARM, Xilinx, AMD, Oracle (Sun), Synopsys, Cadence, Mentor Graphics, Jasper Design Automation and many others to craft an industry-wide.

San Jose, CA

Manager of a team of Application Engineers who worked closely with leading ASIC and SoC design teams (including Sun, AMD, Intel, HP, Cisco, Nortel) to maximize the benefit from using assertions, coverage points and formal verification within simulation-based verification methodologies.

San Jose, CA

A co-founder of 0-In Design Automation, which was a pioneer of the use of assertions libraries for verification of RTL designs. This developed into the assertion-based verification (ABV) methodology now commonly used for functional verification of ASICs, SoCs and processors. While at 0-In, also pioneered the combination of formal verification techniques.

Ph.D, Computer Science

Technical Management Program

M.Eng, B.Sc (Hons), Microelectronic Systems Engineering