Principal Engineer
CurrentAnalog designer working on SERDES development and hard disk drive read channel chips in advanced technologies, from 130nm down to 7nm. Work has included PHYs for PCIE (Gen3-5), SAS (Gen 3/4), and previous generations. Work projects have included AFEs, 100 MHz to 2.5 GHz programmable CTFs, 6-bit 2.5+ GHz ADCs (flash, two step, SAR), 3 GHz low jitter PLLs.