Silicon Engineering Group (SEG)

Microarchitect, designer and unit lead of I6400/I6500 MIPS CPU, a 64-bit, dual-issue, multi-thread processor. Driving continuous product improvement of the MIPS I6400/I6500 family of CPUs.▶ Leading multi-site team in development of next-generation Execution Unit (EXU). ▶ Restructured the EXU microarchitecture, elevating it to the next level of function, throughput, frequency and power.Took the I6400 Execution Unit (EXU) from concept to general customer release in three years.▶ Conceived I6400 EXU microarchitecture, which handles instruction execution from dispatch through graduation. Exceeded single-thread and multi-thread performance goals measured by Dhrystone, CoreMark and Spec benchmarks.▶ Led I6400 EXU design team. Maximized productivity of a multi-site team (UK and Santa Clara) through continuous collaboration. Delivered the EXU comprising 60% of the CPU core and encompassing integer, floating-point, vector, virtualization and system control functions.▶ Individually implemented I6400 EXU scoreboard RTL, which tracks instruction execution, manages instruction interlocks, and handles pipeline flushes.Upgraded MIPS InterAptiv CPU core. Added ECC to level-1 data cache. Delivered to customer and realized $2.4M in licensing revenue.

Developed a family of self-timed digital pulse and clock generation circuits and a self-timed receiver circuit for recovering data from a two-wire communications channel. Granted US patent 8,693,607.For more information on Patent 8,693,607 copy-and-paste this URL in your browser.https://drive.google.com/drive/folders/0BzPNOxoyCBFqNXZ4WndHRDNnWmM?usp=sharing

Architected, designed, verified and taped out Nvidia's PCI Express Gen3 physical layer interface. Represented Nvidia on the PCI-SIG Protocol Working Group.

Led international design team in development of a cost-reduced storage controller chip.

Architected the system bus for a RAID-on-chip storage controller. Designed the bus arbiter and integrated a third-party DRAM controller. Managed outside contract implementation of peripheral interface units.

Architected and led design of three generations of InfiniBand switch chips. Delivered best-in-class performance. Fully functional chips at first silicon. Built company's patent portfolio.

Staff Engineer 1997 - 2000Architected and designed major portions of the second-generation Synfinity Router chip including link training, functional BIST and in-band management. First silicon was functional.Manager 1996 -1997Managed a team of 15 engineers which developed a two-chip bridge from PCI to HAL's Synfinity multiprocessor interconnect. Chips were functional at first silicon.Chief Hardware Engineer 1994 -1996Solved a broad range of systems issues for a multiprocessor server including competitive analysis, configurations, performance, RAS and design team support.