Giacomo Rinaldi

Giacomo Rinaldi Email and Phone Number

Cofounder and VP of Engineering @ Chronos Tech
San Diego, CA, US
Giacomo Rinaldi's Location
San Diego, California, United States, United States
Giacomo Rinaldi's Contact Details

Giacomo Rinaldi personal email

Giacomo Rinaldi phone numbers

About Giacomo Rinaldi

Giacomo has years of proven experience in analog mixed signal design with focus on high speed links. Before joining Chronos Tech, Giacomo was project lead and architect at Intel Custom Foundry working on the latest ultra-high speed multi-standard Serdes in FinFET technology. Giacomo’s breadth of expertise, from architectural definition to high volume manufacturing, are the result of his direct involvement in all aspects of the product life cycle of a chip, having successfully taped out multiple products in BiCMOS, planar and FinFET CMOS technology. Giacomo has a Laurea Doctorate degree in Electrical Engineering and an MBA. He is also the inventor of various US Patent on the electrical field.

Giacomo Rinaldi's Current Company Details
Chronos Tech

Chronos Tech

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Cofounder and VP of Engineering
San Diego, CA, US
Website:
chronostech.com
Employees:
7
Giacomo Rinaldi Work Experience Details
  • Chronos Tech
    Cofounder And Vp Of Engineering
    Chronos Tech
    San Diego, Ca, Us
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  • Chronos Tech
    Vp Of Enginnering
    Chronos Tech Jun 2015 - Present
    San Diego, California, Us
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  • Intel
    Project Lead And Architect
    Intel Nov 2010 - May 2015
    Santa Clara, California, Us
    Part of Intel Custom Foundry I have covered various leading role in the Analog IP path-finding and Serdes group from architecture to production release in fin-FET technology. Specific projects and details cannot be disclose at this time. Responsible for the Production Release Qualification of the 45nm server chipset. Engaged in all the PRQ activity including Electrical Validation, System Validation and High Volume Manufacturing. High Speed IOs/General IPs Coordinator responsible for planning, coordinating and overseeing various IPs in the definition and integration of SoC
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  • Vitesse Semiconductor
    Chip Lead And Architect
    Vitesse Semiconductor Sep 2008 - Nov 2010
    Chip-Lead responsible of system level architecture and design/layout of a quad Backplane EQ/Cable EQ/Re-Clocker/Cable Driver for HD3G/HD/SD video application in 0.13u CMOS TSMC technology.Responsible of design/layout and top level chip integration of various blocks of a 16x16 DC to 11.5Gbps Crosspoint/Signal Conditioner in 0.18u SiGe IBM technology.
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  • Intel
    Staff Analog Design Engineer
    Intel Aug 2005 - Sep 2008
    Santa Clara, California, Us
    Transmitter Lead and architect for two projects: PCIe Gen III (8Gbps) and SAS/SATA (6Gbps) in 45 nm CMOS technology.Successfully taped-out and tested a 6Gbps SAS/SATA PHY hard macro in 90nm CMOS technology.Member of the serial PHY development design team for high speed serial interface applications such as PCIe, SAS and SATA.Responsible for the architecture, mixed-signal behavioral modeling, transistor-level schematic design, functional and electrical validation.
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  • Stmicroelectronics
    Analog Design Engineer
    Stmicroelectronics May 2001 - Aug 2005
    Geneva, Switzerland, Ch
    Projects that were brought to completion and successful tape-out were: (1) A Fast-Ethernet PHY IP: 0.18um process(2) PPECL/LVDS pad 0.18um and 0.13um process(3) PCI-Express PHY IP 0.13um and 90nm(4) SATA 3G Transmitter 90nm
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  • Esaote
    Hw/Sw Engineer
    Esaote Jul 2000 - May 2001
    Genova, Italy, It
    HW/SW Engineer responsible of developing communication layer for medical application.
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Giacomo Rinaldi Skills

Mixed Signal Soc Cmos Ic Analog Circuit Design Analog Semiconductors Verilog Asic Debugging Serdes Simulations Vlsi Electronics Pcie Integrated Circuit Design Circuit Design Signal Integrity Ethernet Cadence Virtuoso Eda Spectre System On A Chip Silicon Integrated Circuits Rtl Design Very Large Scale Integration

Giacomo Rinaldi Education Details

  • Università Degli Studi Di Firenze
    Università Degli Studi Di Firenze
    Telecommunication Technology
  • University Of Phoenix
    University Of Phoenix
    General Management

Frequently Asked Questions about Giacomo Rinaldi

What company does Giacomo Rinaldi work for?

Giacomo Rinaldi works for Chronos Tech

What is Giacomo Rinaldi's role at the current company?

Giacomo Rinaldi's current role is Cofounder and VP of Engineering.

What is Giacomo Rinaldi's email address?

Giacomo Rinaldi's email address is gi****@****ail.com

What is Giacomo Rinaldi's direct phone number?

Giacomo Rinaldi's direct phone number is +160233*****

What schools did Giacomo Rinaldi attend?

Giacomo Rinaldi attended Università Degli Studi Di Firenze, University Of Phoenix.

What skills is Giacomo Rinaldi known for?

Giacomo Rinaldi has skills like Mixed Signal, Soc, Cmos, Ic, Analog Circuit Design, Analog, Semiconductors, Verilog, Asic, Debugging, Serdes, Simulations.

Who are Giacomo Rinaldi's colleagues?

Giacomo Rinaldi's colleagues are Akbar Shokouhi.

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