Overseeing technology development at Smartbike, India's largest public bike sharing company.

Product development for online storefront for small businesses - list product catalog, online ordering and payment.

Led IoT Division with offerings in custom IoT projects, shared mobility, logistics and UAVs

As a part of SoC Performance team, I worked on 2 architectures of memory subsystem (interconnect fabric, last level cache and memory controller) ensuring end-to-end QoS for real time agents,Led to a patent in interconnect design innovation involving urgency counter manipulation in arbitration algorithm.

Worked on 2 taped-out and ongoing premium tier Snapdragon projects Pre-silicon performance analysis of memory subsystem: performed analysis on SoC TLM platform focusing on Quality-of-Service (QoS) and bandwidth efficiency aspects of performance of memory subsystem of upcoming project; Further proposed and analyzed the impact of micro-architectural enhancements for performance bottlenecks identifiedWork with SoC architects, model developers and RTL designers on daily… Show more Worked on 2 taped-out and ongoing premium tier Snapdragon projects Pre-silicon performance analysis of memory subsystem: performed analysis on SoC TLM platform focusing on Quality-of-Service (QoS) and bandwidth efficiency aspects of performance of memory subsystem of upcoming project; Further proposed and analyzed the impact of micro-architectural enhancements for performance bottlenecks identifiedWork with SoC architects, model developers and RTL designers on daily basisResponsible for releases of SystemC based model and well-versed in SoC TLM-based platform used for performance analysisRTL performance analysis: developed perl scripts to extract useful information from FSDB files significantly reducing the time to root cause performance issues related to QoS or efficiencySupport for post-silicon debug issuesLeadership: advised summer intern for automation of performance validation of model, trained new team members on architecture, analysis flows and platform updates Show less

Performance modeling of memory sub-system for Tegra products: - Worked in a global team of 20 and local team of 4 to develop and triage C++ based cycle- accurate model; performed studies to test the impact of various policies on the performance,Adjudged as Top Contributor for the performance in first year at workMicro architecture, RTL Design and Verificiation for modules Image Compositor, security engine and SoC integration in upcoming Tegra projectsUpdated… Show more Performance modeling of memory sub-system for Tegra products: - Worked in a global team of 20 and local team of 4 to develop and triage C++ based cycle- accurate model; performed studies to test the impact of various policies on the performance,Adjudged as Top Contributor for the performance in first year at workMicro architecture, RTL Design and Verificiation for modules Image Compositor, security engine and SoC integration in upcoming Tegra projectsUpdated synthesis flow for new std cell library to be used in upcoming project Show less