Rishav Kumar Email & Phone Number

• Good experience in handling RTL to GDSII implementation including PnR, PV/Timing signoff closure with technology node 32nm.• Completed thorough training in core physical design implementation and sign-off (synthesis, placement & routing , clock tree synthesis, timing convergence, layout closure, EM, IR drop), UNIX, verilog, digital electronics , CMOS technology for a period of 6 months• Hands-on experience in Synthesis, Floorplan, Placement and Optimization, Congestion analysis and reduction (DRC fixes), Timing analysis and fixes (STA) and low power concepts.• Handled RTL to GDSII implementation including Place and Route (PNR), Layout Verification, Timing sign off closure in technology node 32nm.• Exposure to industrial tools from Synopsys.• Good understanding and experience in Scripting languages such as TCL for various automation.

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  Physical Design Trainee

  Takshila Institute Of Vlsi Technologies

  Nov 2023 - Present

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  Ccs (Chaudhary Charan Singh)University Meerut

  7.2