Ritchie Chen Email & Phone Number

Design USB bridge chip (to I2C/SPI): During this period of time, three serious IP bugs were figured out and were solved effectively and efficiently after thoroughly and carefully communicating with Poland’s IP provider. FTDI design flow mainly focuses on verifying all chip functions on FPGA board, which is under my charge. I am responsible for planning, implementation and FPGA verification, providing related data to backend engineers, sometimes I also need to write simple firmware.With… Show more Design USB bridge chip (to I2C/SPI): During this period of time, three serious IP bugs were figured out and were solved effectively and efficiently after thoroughly and carefully communicating with Poland’s IP provider. FTDI design flow mainly focuses on verifying all chip functions on FPGA board, which is under my charge. I am responsible for planning, implementation and FPGA verification, providing related data to backend engineers, sometimes I also need to write simple firmware.With abundant experience on the whole process of asic design flow, I also successfully resolved all problems from firmware team and from board evaluating. This chip was taken good care of and soon to be in mass production this year. Show less

Taiwan

Performance Analysis Software Design: providing a performance review system to ensure our customers the performance of Sonic’s NoC IP architecture can meet or even is better than their product requirement. RTL-POP (performance observation point) was probed into original hardware architecture. After RTL simulation, it will generate SQLite database. We used analysis calculation tool (C++) to process the database into condensed data. Finally, the graphical user interface (Java) provides… Show more Performance Analysis Software Design: providing a performance review system to ensure our customers the performance of Sonic’s NoC IP architecture can meet or even is better than their product requirement. RTL-POP (performance observation point) was probed into original hardware architecture. After RTL simulation, it will generate SQLite database. We used analysis calculation tool (C++) to process the database into condensed data. Finally, the graphical user interface (Java) provides designers the performance analysis results of their hardware architecture.Before this, we also established automatic verification system and which was seamlessly integrated into Sonics’s original infrastructure flow. Show less

Taiwan

Designed Class-D Digital Codec：Co-worked with analog engineers and designed Cmedia digital codec that supports sampling rate from 8 KHz to 192 KHz. All digital design (RTL, synthesis, STA) was done and taken care well under my sole charge. The DAC quality of this IP is 122dB and ADC quality of this IP is 110dB. This design was successful in integration and mass production.Design Equalizer：Implement Equalizer IP to replace Micronas chips in handset and speaker products of Logitech. Even… Show more Designed Class-D Digital Codec：Co-worked with analog engineers and designed Cmedia digital codec that supports sampling rate from 8 KHz to 192 KHz. All digital design (RTL, synthesis, STA) was done and taken care well under my sole charge. The DAC quality of this IP is 122dB and ADC quality of this IP is 110dB. This design was successful in integration and mass production.Design Equalizer：Implement Equalizer IP to replace Micronas chips in handset and speaker products of Logitech. Even more, the IP is more flexible and friendly for users to set the settings of frequency, Q and gain. Show less

Taiwan

Research and designed chips of Timing Controller which was applied to LVDS, RSDS, PPDS and Serdes interface. Furthermore, let more verification skills, AMS Designer, C, Perl, SystemVerilog languages, be applied to hardware designs (Hi-FRC and HDCP). These skills saved verification time and made original verification flow more robust. The precious experience for me was to co-work and communicate with elites from worldwide.

Taiwan

Main research was in RAID system related chips in order to utilize the storage capacity. I was mainly in charge of designing RAID6, DMA, XBUS and PIN&PAD placement of chip. The RAID6 function in chip is a major milestone for Infortrend. This chip was successful in mass production.

Taiwan

During the four-year period in ITRI, I took part in research and design of key technology about Java processor, Java smart card for future electric appliances. We also designed a high performance SOC that combined our Java coprocessor with ARM9 compatible chip (FA526) from Faraday and smart I/O from Prolific. In the last year in ITRI, I indulged in the development of image processor with special architecture of Parallel Arithmetic Block.

Master, Computer Science And Information Engineering

Bachelor, Computer Science And Information Engineering

General