SVP of Engineering & Operations

Vice President (Data Center AI Group) & Director of the Component Hardware Engineering Division responsible for directing the development of datacenter CPUs, GPUs, & AI accelerators for the packaging, power integrity/delivery, signal integrity & thermal-mechanical solutions across a ~$20B revenue businessEngineering Executive for the next-gen Xeon platform across HW, FW & customer enabling

Sr. Director of the Datacenter Component Engineering group responsible for the design and development of all datacenter silicon-packages, the thermal & mechanical solutions for all datacenter components and the power delivery and power integrity solutions for all datacenter platforms.• Built & led the DCE organization (250+ employees) with the goal to create scalable solutions for DCG’s customers for all Xeon® & Nervana® products• Directed the development of component HW solutions for Intel’s next-gen compute, AI & graphics products• Direct engagement with several Cloud Service Provider customers to enable direct innovation via custom solutions

Sr. Director of the Datacenter Power and Package Solutions group responsible for the design and development of all datacenter silicon-packages and the power delivery and power integrity solutions for all datacenter platforms.• Built & led the DPPS organization (160+ employees) from a packaging, power integrity & delivery standpoint for all Xeon® products• Co-architected & led the component HW execution of the Xeon® Cascade Lake – AP product for DCG’s “Advanced Performance” segment

Leading the Platform and Package Engineering Organization that supports the Platform engineering leadership and the Silicon-Packaging for all Datacenter Platforms and CPU, Chipset & SoC silicon ingredients.• Led/Directed the development of over 60 silicon-package designs across DCG’s CPU & Chipset products including Xeon® Phi™, Xeon® E7/E5/E3, Xeon® D & Intel® Atom• Led the intercept of Intel’s 1st PoINT® based packaging architecture for the Xeon® E5 family of products• Led the implementation of Intel’s 1st FIVR designs for Xeon® E7/E5 & D family of products• Engaged in DCG’s Next-Gen Product Development & Delivery initiative and developed the “Derivative Development” methodology for quick-turn product development• Served as DCG’s “Cost Czar” and drove >$500M in savings across the product BOM, test & manufacturing costs• Served as “one-voice” for all new custom silicon programs for the Datacenter Engineering Group in DCG managing the definition, planning, budgeting and hand-off to engineering execution teams

Managed the Silicon-Package design teams in the Datacenter & Connected Systems Group (DCSG) that supported all DCSG's CPU, chipset and other silicon ingredients.• Drove several cross-functional efficiency initiatives and effort reduction across multiple generations of products• Forged key relationships with stakeholders across silicon design, technology development, manufacturing & test• Developed a cross-functional platform engineering & technology engagement model and product design methodology

Led the Silicon-Package design for various CPU, chipset and other silicon ingredients in the Server Products Group.• Developed 10+ Xeon® CPU & chipset silicon-packages including Intel’s 1st Integrated Memory Controller CPU: Nehalem

Supported the package design for various automotive components including smart connectors and other automotive modules• Lead Engineer on the “Smart” Connector program developing IC packages for smart switches & controllers resulting in the reduction of the wiring harness in automobiles• Project Engineer on the Gen-III Ignition Control Module supporting the design modification of the module for a 20% reduction in product cost. Conducted reliability & qualification testing of the ignition module.