Rob Jeschke Email & Phone Number

Designed and coded a light-weight Python web user interface for running production verification test suites, using webpy, to be used at contractor production facility.Wrote Python code to capture DTMF cue-tone and cue-trigger data using an AccesIO data capture card. Implemented Python code to carryout FFT analysis on captured DTMF cue-tone data to verify correct tone frequencies.Administered/managed FPGA group's build and simulation environment including user support, bug fixes, tool updates/patches, and documentation. Tools managed: Xilinx Vivado, Synopsys VCS Cadence's BluePrint FPGA I/F generation tools.Designed, Implemented, and Administered/managed FPGA group's LAB test racks.Administered the FPGA group's FPGA design VMs. This included managing the design tool licenses, user accounts, debugging tool issues, providing user support for both the design tools and linux environment, and support for remote access tools.Managed/administered the FPGA group's Git revision control system repositories.Managed/administered the FPGA group's FPGA MySQL release database.Managed/administered the transfer of user accounts, design data, and design environments (approx. 10TB) from Cisco to Synamedia.

Administered the FPGA group's design VMs, design tool licenses, user accounts. Debugged tool issues, providing user support for both the design tools and linux environment, and support for remote access tools. Created bash scripts to automate tasks such as user account creation, disk space allocation, and user environment creation.FPGA designer for MPEG transport FPGAs.Managed/administered the FPGA group's CVS revision control system repositories.Coded/administered the FPGA group's internal web pages. Installed/mplemented “Twiki” wiki to facilitate collaboration between FPGA, hardware, and software groups at various international locations.

Tested analog video outputs on Scientific Atlanta satellite receiver products using test equipment such as a Tektronix VM700A for both NTSC and PAL video.FPGA designer for MPEG transport FPGAs and ASICs, predominantly in VHDL. Designed/coded various modules for receiving, locking too, and decoding MPEG transport streams over RF and ASI.Administered the FPGA group's design servers. This included managing the design tool licenses, user accounts, debugging tool issues, providing user support for both the design tools and linux environment, and managing the archiving and backup of design data.Created and carried out FPGA engineering verification tests including automated testing.

Bachelor Of Applied Science - Basc, Electrical Engineering

Master Of Applied Science - Masc, Computer Engineering