Managed IC development team of two senior engineers and one technician in development of intelligent LED lighting controller ICs from specification through production. Responsible for hiring, project management, and technical management of Chinese development partners. One mixed-signal control IC design completed and in production and second analog control IC design completed.In addition to management duties, was system architect for both ICs and an individual contributor in IC design. Responsible for digital function specification, analog block specification, analog IC design, verification and layout review. Project management and technical interface to our Chinese IC IP and backend team and made frequent trips to China to meet with the Chinese team in person.Developed internal automated test system to test chip function over complete operating range. System used to ensure design performance and for QC testing of production samples. Performed statistical analysis of QC and production data to ensure yield.Designed automated part handler in Autodesk Fusion 360 to automatically test packaged parts at -30C. Built system including CNC machining custom parts. Machine removed chips from reels, inserted chips into test socket, ran automated tests, and binned chips based on test results. System has a throughput of one chip per minute and has tested >30k chips.

Created development and deployment plan for a Bitcoin mining system including specifying tasks and resources needed to complete systems from design through installation. Built team of five experienced engineers and eleven technicians and managed the day-to-day operations of system design, manufacturing, installation and maintenance. Responsible for development of software, firmware, Verilog, mechanical and thermal systems. Developed detailed technical specifications for each area of the system and was actively involved in design and problem solving. Redesigned both main processor board and multi-phase power supply system using chips from new vendors to avoid part supply shortages. Rewrote system Verilog for new hardware including SPI subsystem and a 256 channel, maskable priority interrupt controller.Managed manufacturing in both Asia and Oregon.212TH/s of completed mining systems installed in three major datacenters with first deployment within 4 months and all system installations completed in 6 months. The systems are installed in standard 19” server racking and consume a total of 1.3MW of power.Wrote python code using numpy and scipy modules to model statistics of Bitcoin price fluctuations.

Power system architect and lead hardware designer for high volume, consumer audio products that meet exacting audio performance, battery life, cost and thermal requirements. Responsibilities included system analysis and design, part selection for cost and performance, debug and test, thermal and EMI performance and design for manufacturability.Worked closely with firmware and chip designers to ensure system functionality and performance and created test plans to verify hardware performance. Worked with team to redesign first generation product power system to increase quiescent battery life by >50%, meet EMI and reduce maximum system temperature resulting in a significantly improved user experience. Analyzed existing power system, determined areas of improvement and worked with the team to implement changes. Created rules of thumb and simple Excel spreadsheets for high power battery powered audio power systems design to make power system component selection easier.Designed second generation hardware platform using a new DSP chipset and re-architected power system resulting in significant cost savings and improved system performance including extended battery life and better EMI behavior. New hardware design used as a platform for all new designs in the business unit.Assisted Asian manufacturers with design transfer, first article inspection, test and debugging. Helped manufacturers design production test plans that provided maximum test coverage with minimum test time and equipment.

System engineering group leader. Make key contributions to company standards, system design, algorithm development and energy-harvest improvement technologies. Contributed to technology development and patent applications in the areas of power conversion architectures, IEEE 1547 grid disconnect standards, power optimizer algorithms and system optimization.Provide technical expertise at VC meetings with company CEO. Responsible for developing and presenting technical presentations and answering technical questions from both laypeople and technical experts.Provide technical training to new Product Assurance engineers, work to ensure tests developed provide excellent test coverage and that the finished product provides an excellent customer experience.Work closely with marketing and engineering to guarantee that specifications are aligned and feasible within time, budget and product cost constraints. Work with Product Assurance group to help define acceptance tests for products.Develop functional specifications for power optimizer, AC module and communications gateway products.Lead engineering group in developing, testing and productizing Maximum Power Point Tracking (MPPT) and inverter interaction algorithms for all power optimizer products while meeting tight deadlines and budget requirements.Drive next generation of MPPT and inverter interactions algorithms.Develop system simulation tools in Matlab and C# to simulate Photovoltaic (PV) system behavior including PV module physics, shadow and mismatch modeling, and inverter function. Used these tools to develop, test and optimize algorithms.

Visited customers in Europe, Asia and US to understand customer needs and support product definition and to provide effective customer support for engineering samples and test sites. Customer support included education, system installation and troubleshooting, and test result explanations. Developed test plans tailored to each customer site to demonstrate the function and value of power optimizer products. Worked closely with VP of Marketing/Business Development to create datasheets and other marketing documents. Worked with management to develop ROI/LCOE calculations for Azuray products.Developed Excel, Matlab and C# programs to analyze both laboratory and field site test results and routinely presented findings to engineering and management.Designed and wrote unique-to-industry PV shade simulation software in Microsoft Visual C# .NET for customer visits and tradeshow booth demos at SPI, SNEC and Intersolar Germany/North America. Interactive touchscreen display simulated shading effects in real-time to show the benefits of Azuray power optimizers on PV systems.Wrote application notes and product manuals for the power optimizer product lines. Worked with technical writers to develop installer and end-user manuals for communication gateway product.

Contributed to all areas of the company including product design and development, marketing and sales of the WavyWand™ product. Product featured in HGTV’s 2006 Holiday Toy Special.Developed the company webpage including the store front and integrated the PayPal cart and payment systems.Wrote a C++ program for Windows XP in which users could create their own text, drawings and animations and upload them to the WavyWand™.Developed an MP3 player with integrated GPS, heart rate monitor and battery control hardware. Architected the product, designed the schematic and PCB and wrote software in assembly and C/C++ on the Atmel AVR platform. Worked closely with a mechanical engineer to ensure that the product would fit in a custom designed case.Worked with a mechanical engineer to create a CNC-controlled milling machine. Wrote RTLinux drivers to the interface with the digital IO card.

Managed the graduate student analog/mixed signal research laboratory.Specified equipment to be ordered for the lab and maintained over $1M of test equipment.Trained new students on the use of equipmentAssisted graduate students with troubleshooting and testing.Taught PCB layout and design class for graduate students.

Developed a novel parallel delta-sigma analog-to-digital converter architecture. Designed, implemented and tested a high-speed, high-resolution parallel delta-sigma analog to digital converter in TSMC 0.25um. The ADC produced 13.8 bits of resolution with a 4X OSR and a sample rate of 100MS/s.Developed a closed-loop BiCMOS track-and-hold in a SiGe process. The architecture provided both high linearity and high speed, with 98.7dB SNDR at 50MS/s and 89.4dB SNDR at 100MS/s.

Developed channel calibration algorithm for a parallel delta-sigma analog-to-digital converter.Tested and redesigned a 14-bit 800kHz pipelined delta-sigma data converter.Maintained computer systems and lab test equipment, including providing support services to other graduate students and ordering equipment.Co-developed a selective anisotropic silicon etching process using TMAH.Designed and built a direct-write laser system for patterning photoresist to allow post-processing on packaged integrated circuits.Designed high-voltage transistors in standard CMOS processes and used Ample script in Mentor Graphics to automate layout of transistors

Designed and implemented hardware, firmware and software for factory automation and data acquisition.Analyzed product flow on poorly functioning palletizing machine. Redesigned and rewrote PLC program to create a functional machine. Optimized flow for speed and reliability and worked closely with a mechanical engineer to implement the redesign, which resulted in 400% increase in product throughput and a 300 times reduction in product breakage.