Robert Corley Email & Phone Number

Palo Alto, California, Us

Avago acquired Emulex in May 2015, then merged with Broadcom

Block lead for transmit pipeline for Converged Network Adapter (CNA) ASIC family. Responsible for micro-architecture, RTL design, and verification. Supported existing products, performed ECOs, and developed micro-architecture and RTL for new designs. Tracked project schedules and mentored junior engineers.

Austin, Tx, Us

Design engineer for Lifesize Passport and Passport Connect endpoint products as well as Lifesize Bridge. Responsible for RTL design and verification of various design functions such as GUI overlay and alpha-blend, SD flash, memory interface, and MJPEG decoding and video processing. Interfaced with software team and debugged issues in the lab.

Santa Clara, California, Us

Team lead for XML accelerator IP for Intel. Responsible for micro-architecture and RTL development of cache and interface design. Selected PCI Express IP and converted existing design from PCI-X to PCIe for both FPGA emulation and ASIC. As team lead, coordinated development effort among designers and tracked schedule. Attended Intel-internal PCIe 3.0 conference to discuss new specification.

Us

Micro-architecture specification, RTL design and unit verification of the host interface and output generator units for XML/XSLT hardware accelerator ASIC. FPGA emulation lead responsible for chip top-level design, platform bring-up, debug and FPGA team coordination.

Design engineer for 2.5G network processor ASIC chipset, as well as APP550, APP650, and APP350 network processor ASICs. Responsible for RTL design, synthesis, timing, and memory BIST. Responsible for host interfaces, DMA engines, policing and statistics logic, and network processor to on-chip ARM interface through AMBA bus. Prototyped designs in FPGAs and supported lab bring-up.

Houston, Texas, Us

Team lead for 64-bit PCI host bridge ASIC for the HP V2500 server. Responsible for Verilog design and synthesis of RTL into gates. Also responsible for physical design of the ASIC to do the floorplan, placement, and routing. Performed ASIC bring-up in the lab and the debug of PCI hardware and software. Participated in PCI-X 1.0 specification workgroup with engineers from HP and other companies.

Designed and tested PCI host bridge ASIC for SPP2000 server and PCI to Mbus bridge for SPP1600 server. Responsibilities included Verilog design, design synthesis, verification, and lab bring-up. Also qualified SCSI disk, tape, and bus adapters on the SPP1000 server and worked with vendors to resolve issues.

Bsee, Engineering

Msee, Engineering