Robert Liner Email & Phone Number

Chapel Hill, Nc, Us

Williston, Vt, Us

Physical design and verification of analog circuits on custom chips, some with high content of RF features. Working in130nm, 22nm and 2nm technologies.

San Jose, California, Us

Physical design and verification of custom analog and mixed signal circuits for SerDes and DDR projects. Responsibilities include methodology development, floorplanning, block-level layout, top-level construction, full chip verification and final delivery. Leading team members worldwide to ensure a high quality product and to meet committed schedules. Project layout lead for multiple successful DDR programs. Experience in Intel (14nm), TSMC (28nm, 16nm, 10nm and 7nm) and Samsung (7nm and 14nm) design technologies.

Phoenix, Arizona, Us

Worked with Analog design engineers to create/modify/verify layouts of analog circuit blocks including: Band Gap, Modulator, Voltage Regulator, Current Limiter, and ADC (3-AL BiCMOS/DMOS, 0.35um process)Using Cadence VirtuosoXL tools and Assura verification flowsInvolved in several shuttle projects from floor planning stage through mask request flow (4-Al BiCMOS/DMOS, 0.18um process)Comfortable working with engineers at multiple locations and time zones

Kista, Stockholm, Se

Took over layout responsibility of a sub-section of a radio transceiver project (5-Al BiCMOS process, 0.25um CMOS)Worked closely with IC design engineers to create/modify/verify layouts of circuit blocks including: LNAs, Mixers, Gain Switch, pad ring and top level floor planExecuted analog radio transceiver block layout and verification: crystal oscillator, ADC, DigRF interface (90nm CMOS)

Munich, ., De

Constructed, modified and verified new and existing digital/analog custom layout according to schematics of circuits used in 90, 65 and 58nm RAM productsAssisted in creating new 65nm standard cell/block libraries for current and future RAM productsUsed Cadence Virtuoso tool, data management with Design Sync, Assura and Calibre verification flows

Koto-Ku, Toyosu, Tokyo, Jp

Executed successful schematic translation, custom layout (Digital/Analog) and verification of a wide variety of integrated circuits used in microcontrollers including voltage down converter, AD converter, ICU, RAM, PLL and I/O drivers using standard cells and custom CMOS logic structuresAuto-routed full chip power and signal routing using Cadence chip assembly routerVerified and debugged full chip checks including LVS, DRC and ERCManaged daily tasks for entire layout team and initiated reviewsCollaborated with CAD members on developing scripts and tools that improved efficiency and reduced errorsTrained and supervised new members of the layout teamLed the layout team on six successful MCU projects, team member on ten others. Typical project: 16-bit Microcontroller, 0.2um 3-Al CMOS Process with 132kB Flash / 12kB RAMUsed Mentor Graphics IC Station, Cadence CCAR, Calibre and Dracula verification flows