Senior Mask Designer
CurrentPhysical design and verification of analog circuits on custom chips, some with high content of RF features. Working in130nm, 22nm and 2nm technologies.
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@asicnorth.com
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Robert Liner is listed as Senior Mask Designer at ASIC North at ASIC North, based in Raleigh-Durham-Chapel Hill Area, United States, United States. AeroLeads shows a work email signal at asicnorth.com and a matched LinkedIn profile for Robert Liner.
Robert Liner previously worked as Senior Mask Designer at Asic North and Lead Design Engineer at Cadence Design Systems. Robert Liner holds Bachelor Of Arts (B.A.), Multi-Disciplinary Studies Concentration Title: Graphic And Business Communications from North Carolina State University.
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Integrated Circuit layout designer with an extensive 25+ year background in full custom analog and mixed signal physical design. Proven team leader from methodology development through final delivery. Comfortable working with team members across NA and worldwide. Highly organized with exceptional communication skills.
Listed skills include Cmos, Physical Design, Cadence Virtuoso, Semiconductors, and 17 others.
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Williston, VT, US
Physical design and verification of analog circuits on custom chips, some with high content of RF features. Working in130nm, 22nm and 2nm technologies.
San Jose, California, US
Physical design and verification of custom analog and mixed signal circuits for SerDes and DDR projects. Responsibilities include methodology development, floorplanning, block-level layout, top-level construction, full chip verification and final delivery. Leading team members worldwide to ensure a high quality product and to meet committed schedules..
Phoenix, Arizona, US
Worked with Analog design engineers to create/modify/verify layouts of analog circuit blocks including: Band Gap, Modulator, Voltage Regulator, Current Limiter, and ADC (3-AL BiCMOS/DMOS, 0.35um process)Using Cadence VirtuosoXL tools and Assura verification flowsInvolved in several shuttle projects from floor planning stage through mask request flow (4-Al.
Kista, Stockholm, SE
Took over layout responsibility of a sub-section of a radio transceiver project (5-Al BiCMOS process, 0.25um CMOS)Worked closely with IC design engineers to create/modify/verify layouts of circuit blocks including: LNAs, Mixers, Gain Switch, pad ring and top level floor planExecuted analog radio transceiver block layout and verification: crystal.
Munich, ., DE
Constructed, modified and verified new and existing digital/analog custom layout according to schematics of circuits used in 90, 65 and 58nm RAM productsAssisted in creating new 65nm standard cell/block libraries for current and future RAM productsUsed Cadence Virtuoso tool, data management with Design Sync, Assura and Calibre verification flows
Koto-ku, Toyosu, Tokyo, JP
Executed successful schematic translation, custom layout (Digital/Analog) and verification of a wide variety of integrated circuits used in microcontrollers including voltage down converter, AD converter, ICU, RAM, PLL and I/O drivers using standard cells and custom CMOS logic structuresAuto-routed full chip power and signal routing using Cadence chip.
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Robert Liner works for ASIC North.
Robert Liner is listed as Senior Mask Designer at ASIC North at ASIC North.
AeroLeads has found 1 work email signal at @asicnorth.com for Robert Liner at ASIC North.
Robert Liner is based in Raleigh-Durham-Chapel Hill Area, United States, United States while working with ASIC North.
Robert Liner has worked for Asic North, Cadence Design Systems, Fairchild Semiconductor, Ericsson, and Qimonda, Inc.
You can use AeroLeads to view verified contact signals for Robert Liner at ASIC North, including work email, phone, and LinkedIn data when available.
Robert Liner holds Bachelor Of Arts (B.A.), Multi-Disciplinary Studies Concentration Title: Graphic And Business Communications from North Carolina State University.
Robert Liner is listed with skills including Cmos, Physical Design, Cadence Virtuoso, Semiconductors, Ic, Drc, Asic, and Cadence.
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