Robert Moss Email & Phone Number

Fort Collins, Co, Us

• Enterprise SSD controller systems architecture.• Primary architect for next generation NVMe placement architecture.• Focus on innovative NVMe features and performance.

Fremont, Ca, Us

Enterprise SAS and PCIe/NVMe SSD controller architecture• Evaluate impact of NMVe standards committee TPAR to enable controller intercepts (CMB, PMR, Sets, IOD, ZNS, KV, Key per IO)• Drafted framework for scalable security architecture• Defined HW automation extensions to enable TCG-NVMe support• Reed Solomon Interleaving to enable Page and Die Kill• Drove architectural Si convergence to reduce HW and FW fragmentation across roadmap• Defined next-generation enterprise controller HW requirements• Worked with engineering leads to define block level architectures and requirements• Championed forward thinking controller features• Oversaw E2E error handling and error framework for consistent testable behaviors & implementationEnterprise SAS and PCIe/NVMe SSD controller design• Design lead for write path covering compress/encrypt, packing, RS, headers, and scrambling• Implemented AgileSoC development methodology across RTL & verification teams• Microarchitecure, documentation and RTL design for dynamic size block tiling• Design lead for FTL ASIC and RTL design for PCIe endpoint application layerNew and emerging market solutions• Developed scalable HW architecture for object oriented drives• Created MMC and CE-ATA bridge ASIC for ultra-mobile consumer electronics HDD• Created HW accelerated verification environment for long-integer arithmetic RSA operations• Defined port hardening requirements for self-encrypting drives

San Jose, Ca, Us

Security subsystem for set-top box controller• Worked with cross-functional team to architect an adaptable security subsystem• Hardware / firmware tradeoffs for cryptographic solutions and system security• Technical lead for security subsystem and embedded / MCM NVRAM solutions• Design and verification of security features to enhance a digital TV standard productConfigurable multiport memory controller• Lead architect for a configurable multiport memory controller• Technical lead for performance optimized DDR controller and AHB interface enhancementsMIPS TinyRISC core• Oversaw DFT, STA and skewed process characterization efforts

Houston, Texas, Us

Embedded Coldfire ASIC for flatbed image scanner• Created system simulation environment and designed SDRAM controller• Established CoSim environment for embedded firmware developmentMultiprocessor embedded ARM ASIC for mobile image scanner• Adapted paper fiber tracking algorithms for hardware implementation• Architected system with multiple embedded ARM processors• Designed Contact Image Sensor controller and signal processing datapathASIC and prototypes for mobile image scanner• Championed emulation and acquisition of Quickturn system• Created portable scanner prototypes using FPGAs and various processors• Spearheaded HP Greeley transition into RTL design methodologyData compression and optical character recognition • Implemented and verified optical character recognition datapath• Adapted optical character recognition algorithms for hardware implementation• Layout, functional and timing verification of LZ data compression ASIC

Master Of Science (Ms), Electrical Engineering

Bachelor Of Science (Bs), Electrical Engineering