Robert Nickerson Email & Phone Number

Chandler, Az, Us

Chandler, Az, Us

Santa Clara, California, Us

Santa Clara, California, Us

• Directing concept definition and early process and assembly development of Intel's next generation of packaging assembly and process development.

Santa Clara, California, Us

• Led assembly and process development as the senior program manager for Intel's First “Foveros” multichip product with 3D interconnect technology with Thru Silicon Via, Responsible for developing both wafer level assembly and package assembly for the Meteor Lake and Arrow Lake family of Processors with combinations of both internal and external silicon.• Directed a large development program to successful completion from product concept through multi factory transfer and HVM.• Key technical decision maker and mentor with weekly presentations to customers and Intel senior management on process and technical progress and indicators.

Santa Clara, California, Us

• Managed Intel's first stacked die TSV package with package on package (POP) memory. Successful completion of product certification and HVM transfer.

Santa Clara, California, Us

• Led process and assembly integration engineering with a focus on coreless substrates products for strip and unit level assembly.• Worked on embedded die and internal/external silicon, developing key building block technologies.

Santa Clara, California, Us

• Led HDI Pathfinding and Design integration development for FCBGA/FCMMAP.• Led the design integration team for Low density package integration including Wire bond MMAP, PBGA, POP, and FSCSP.• Responsibilities included reviewing all test vehicle certification strategies, test chip strategies, data analysis, DOE plans, technology design rules and specs for all LDI technologies to support platform technology certifications.• Led LDI Design Integration packaging for Application and Communication Processor Division supporting both die stack and package on package architectures.

Santa Clara, California, Us

• Led design integration activities for Folded Stack CSP and Stacked Package CSP for P8x5 silicon process.• Closed all Technology Target specs and architecture plans for Process P8x5.

Santa Clara, California, Us

• Oversaw substrate design rules and development for wire bond MMAP stacked die and single die products for Logic and memory, small form factor Flip Chip MMAP, and Multi-layer Flex Tape packages.• Managed Quality Audit Team for ISO 9001 Compliance.

Santa Clara, California, Us

• Handled Product and Test vehicle Substrate Design for HVM and Development PBGA's, VFBGA, and SCSP for BT core MMAP products.

Arlington, Va, Us

• Mechanical Antenna & Microwave MMW Design Department.• Responsibilities included lead mechanical designer for advanced technology program with concentrations on hardware design, fabrication, system integration, thermal considerations, and designs for manufacturability.• Other responsibilities included supervisor and mentor for new hire mechanical engineers, coordinating fabrication of components, vendor support, customer presentations, design reviews, cost and schedule estimates.

Arlington, Va, Us

• Mechanical Antenna & Microwave MMW Design Department• Mechanical Design support on a variety of government contracts• Responsibilities included modeling and preparation of released level three data packages, mechanical fixtures and test equipment, and assisting in hardware development.

Master Of Engineering - Meng, Mechanical Engineering

Bachelor Of Engineering - Be, Mechanical Engineering- Emphasis In Fluid Sciences. Deans Honors (4). Teaching Assistant.