Not actively seeking work, but still open to renewing old connections

Will provide all aspects of Integrated Circuit design including system definition, complete chip design, high level simulation, analog blocks, and digital logic. Will work on a small functional block to get your chip to market sooner. Can assist you on finding a process to best meet your requirements. Give us a call for a quote.

Project lead for the first "UNI/O one wire EEPROM. Invented new circuits and system concepts required for the EEPROM to communicate over one wire and fit in a 3 pin SOT package. See details at http://www.microchip.com/ParamChartSearch/chart.aspx?branchID=70104&mid=&lang=en.Project lead for 1Megabit SPI EEPOM. Invented several circuits required in order to meet design goals. First pass was functional and sampled.Also designed a 4k, 8k, 16k, 32k, 256k, serial I2C EEPROMS.

Designed a motor control device (SA56) that drives DC motors at 60 volts and 5 amps. Designed a high temperature and short circuit shutdown circuitry. Also a Output current measurement circuit that output on a separate pin 0.02% of the current that flowed thru the 5 amp bridge. Other circuits designed -analog to pulse width modulation, current source, and voltage reference.

Member of a team of four engineers that designed the world's only single chip DSP hearing aid. The first and second generation hearing aid chips have propelled Sonic Innovations to a world wide sales of approximately $100M a year to become the fastest growing hearing aid company in the world. During the design of all three generations of hearing aide the following engineering tasks were completed: Designed a Delta Sigma DAC that generated a pulse rate modulated output… Show more Member of a team of four engineers that designed the world's only single chip DSP hearing aid. The first and second generation hearing aid chips have propelled Sonic Innovations to a world wide sales of approximately $100M a year to become the fastest growing hearing aid company in the world. During the design of all three generations of hearing aide the following engineering tasks were completed: Designed a Delta Sigma DAC that generated a pulse rate modulated output Implemented an interpretative filter that uses a CPU structure to eliminate the need for a multiplier. Used only 60% of the area and 50% of the power of the conventional approach. Defined and implemented a proprietary I/O interface that is used to program hearing aides. Designed a 262k EEPROM circuit that operated down to 1.1v. Major contributor in design of three generations of Sonic hearing aides. Show less

Owned and operated a contract design firm. Performed both IC and chip layout. Completed several IC's with OP amps, capacitor filters, Bandgap circuits, DACs, charge pump and analog delay lines. Analyzed standard cell and gate array failures and improved models to avoid future timing problems. Designed major blocks for microprocessors.

Designed several static RAMs. Project engineer for 1kx16/18 asynchronous and synchronous SRAMs. Originated method of implementing synchronous and asynchronous 5volt or 3 volt, 16 or 18 I/O with the same mask set saving approximately $80K in mask cost. Conceived several circuit techniques to improve access time and save power. Patented technique for wafer burn in for "know good die" program.

Managed several engineers were doing SPICE analysis, logic modeling and improving routing techniques for gate arrays.Supervised projects to provide CAD data bases for logic and timing simulation for four gate arrays. Conceived algorithm for estimating loading capacitance before routing for accurate timing model.

Specified design engineering software such as symbolic layout editor, schematic entry, on-line design rule checker, on line continuity checker, and logic simulator. Wrote macros and process definition files in C. Demonstrated and trained CAECO software to customers.

Established a design center in Utah. Hired and trained a staff of 23 engineers and layout designers. Purchased computer design hardware and software for the design department. The "8049 series micro-controllers(8048, 8049, 8050, 8041, and 87p50) were designed. These products were faster, lower power, and smaller die size than the first source. A complete CRT terminal on a single chip was also designed

Member of an engineering team that designed the MK3870 and the MK3872 single chip micro-controllers. Developed new stacked ROM technique that allowed the MK3872 to have 4kx8 ROM. Co-designer of the MK4096( first DRAM with multiplexed addresses. Developed many circuit techniques necessary for high density dynamic RAMs.