Worked on re designing and implementation of Zeroization FSM logic on the KG-250A. Created Test benches and debugged Alarm problems on Cryptographic units. Debugged hot and cold temperature problems affecting Cryptographic units. Supported production on KG-250 units.

Worked on verification of an EDAC circuitry in an Electronic Control Box for an APU unit. Wrote verification reports and created test stimulus for UUTs.

Worked on porting legacy ASICS to Xilinx FPGA. Simulated, Synthesized, and Debugged RTL code in FPGA circuits using Modelsim and Synplicity. Designed GPIB interface controller in VHDL. Created Client Server style Bus Functional model used in VHDL Test Benches.

Designed the digital logic on FPGAs for a VXI based digital video translator and generator for RS-343 video display for the Japanese F-2 aviation systems. Redesigned obsolete ASICS into FPGA in measurement systems for the USAF F-16 ATE systems.