- Created new optimized design flow on MIT Lincoln Labs PDK for 20nm process for AFTX07 chip using Cadence Genus, Innovus, Virtuoso: wrote placement optimization script to reduce routing congestion, increased timing performance,implemented early power rail analysis for reliable power efficiency, reduced IR drop, implementing automations for streamlined verification, improved tapeout efficiency and quality- Designed and implemented I2C and UART interfaces for IO, communication, and data… Show more - Created new optimized design flow on MIT Lincoln Labs PDK for 20nm process for AFTX07 chip using Cadence Genus, Innovus, Virtuoso: wrote placement optimization script to reduce routing congestion, increased timing performance,implemented early power rail analysis for reliable power efficiency, reduced IR drop, implementing automations for streamlined verification, improved tapeout efficiency and quality- Designed and implemented I2C and UART interfaces for IO, communication, and data transfer on AFT-X06 test board- Built custom STM32 Bluetooth shield for AFT-X06 test board that enables efficient communication and data exchange Show less

- Developed nominal photolithography process for 1um transistor feature size, achieving 91% yield rate on 4” wafer. Specialized in mask layout, photolithography, and characterization ensuring process precision and repeatability- Learned to design custom wireless messaging ASIC with GPIO and Wishbone bus for efficient communication protocol. Applied OpenLane tools for synthesis, floorplanning, routing, GDSII generation to meet area, power, timing constraints and developed test benches to… Show more - Developed nominal photolithography process for 1um transistor feature size, achieving 91% yield rate on 4” wafer. Specialized in mask layout, photolithography, and characterization ensuring process precision and repeatability- Learned to design custom wireless messaging ASIC with GPIO and Wishbone bus for efficient communication protocol. Applied OpenLane tools for synthesis, floorplanning, routing, GDSII generation to meet area, power, timing constraints and developed test benches to verify design and integrated project onto FPGA for functional demo Show less

- Co-directed 50-member team to provide free robotics and STEM classes, workshops, and summer camps, to 1500+ underprivileged students - Developed robotics education program with schools in Mali through ACFA- Acquired sponsor funding and credits from 5 companies

Cornfield Lab

Mentored by Dr. Dmitry Zubarev. Developed autoencoder and LSTM with Bayesian optimization to enhance polymerization synthesis prediction using chromatogram patterns, improving predictive accuracy and process efficiency for industrial applications in material science.