• Ported GPU firmware from ARM to RISC-V architecture and maintained the git repository for a future generation GPU. • Maintained the toolchain and validation infrastructure for advanced CPU development for next generations of Intel programmable dGPUs.

• Developed new infrastructure tools for processor power simulation of an Intel Core processor using Python and shell scripting.• Tuned IPC and Power for a future Intel Core processor in a simulation environment.• Ported an old benchmark framework to use a new toolchain and new ISA instructions using Perl.• Developed a Python script to automate rollup of performance metrics from nightly benchmarks for analysis by processor architects.• Performed performance analysis of nightly benchmarks run under dynamic binary translation.• Worked on performance validation for benchmarks run on Intel Atom simulators.Implemented AVX512 microcode flows for an Intel Atom processor simulator.• Worked on setting up Simics images to be used for generating snippets of traces of real applications that can be used in simulation to estimate performance of applications.

• Worked on performance analysis of benchmarks run on the Soft Machines Shasta silicon under dynamic binary translation.• Provided simulator infrastructure support for legacy Soft Machines Shasta simulators, primarily done in C++.• Ported Soft Machines’ Shasta VISC simulators and tools to a new, drastically different version of the VISC ISA.

• Interfaced between hardware and software teams for simulator support. Work done in C++, Python, Ruby and BASH.• Implemented new ISA instructions and simulator support using C++.• Cleaned up a significant amount of legacy simulator code, which required rewriting some portions of microarchitectural implementations, primarily done in C++.

• Brought up servers for use in data centers. Work included bios standardization, OS tuning, and system health monitoring using Python and BASH.• Analyzed performance of low level database software running on the server used for data storage.•

• Ported AMI’s BMC firmware for use in Calxeda’s chassis management controller (CMC). Work done in C.• Developed Calxeda’s network fabric SDK in C/C++.

• Developed testbenches for Sonics’ configurable network fabric technology in System Verilog UVM.• Developed a Java RCP application as part of a team of engineers used for configuration of Sonics’ configurable network fabric technology using Eclipse’s EMF plugin. Maintained the network topology description language parser using XText.

• Developed early prototype toolchains, simulators and tools for Soft Machines’ VISC processor. I also demoed them in multiple VC meetings used to secure funding.• Developed dynamic binary translation JIT optimizations in early prototypes of Soft Machines’ VISC processor.• Along with another team member I designed and implemented a table driven architecture definition framework that connected all teams that depended on the ISA definition in a reliable and automated fashion. Provided related support to guarantee needs of each team were met in a consistent way.• Implemented early FPGA transactors for Soft Machines’ VISC architecture FPGA emulator.• Designed and implemented code to automate the generation of hardware and software decoders driven by the formal table driven architecture definition that I built.

Teaching assistant in the Electrical and Computer Engineering Department. Courses included: Embedded System Design, Computer Architecture and Digital Systems.