Deploying the next generation Pro-FPGA prototyping software and hardware solutions for the applications engineering team. Research and Development for the improvement of the EDA tool that enables FPGA state-of-the-art design methodologies.Deployment of Veloce Prototyping System (VPS)

Development of FPGA mixed-signal prototypes currently working for Research and Development on the next generation Healthcare MRI RF technology. • Design, development, simulation, test, and debug FPGA RTL code supporting a Software Defined Radio (SDR) implemented on Xilinx Zynq MPSoC and Zynq RFSoC Integrated with Petalinux and Pynq framework. • Development and characterization of data acquisition systems by manipulating/analyzing large datasets with Python.• Debug of Xilinx Embedded Flow for ARM embedded processor in FPGA Ultrascale+ technology• Development and troubleshooting of embedded targets using an oscilloscope, logic analyzer,and Vivado Integrated Logic Analyzer (ILA/JTAG).• Wrote engineering documentation such as software and hardware specification.• Provide accurate forecasts of work effort and communicate implementation risks and designtrade-offs to peers and team members;• Collaborated in a team of engineers, architects, and scientists to deliver multi-part product capabilities.

Collaborated as part of the Plexus Design Center on the Development of digital designs and testbench environments usually implemented for FPGA-based products for internal and external customers, from idea concept to production, supporting the full product life cycle activities.Interface to serve customers and global cross-functional teams to deliver Hardware and FPGA solutionsDigital and FPGA design as well as Testbench.Timing analysis Simulation & VerificationHDL coding ( Verilog, System Verilog)FPGA Prototyping

Created Emulation/FPGA Prototypes for validation of SoC/ASIC Architectures and Early Software validation.Performed Compilation, Synthesis, Partitioning, and Place and Route with Protocompiler and Vivado for FPGA Bring-Up on Synopsys HAPS 70/80 platforms. Functional Simulation and analysis on OVM environment using VCS & DVE.Defined RTL changes required for emulation/FPGA Implementation.Developed Hardware and Software collaterals for integration such as script automation for data analysis.Solved critical synthesis and implementation problems on FPGA Ultrascale+ such as Timing closure, CDC, Routing Congestion, Bitstream Generation, Constraint Implementation for Turn around time improvement.Engineering Documentation.Mentorship and Training of co-workers.Collaboration with Application Engineers, Sales, Tooling & Management to select the appropriate tools and flows for emulation.

Development and Debug of SoC architectures in OVM Environment, specialized on test cases, BFM, Transactors, TLM, SystemVerilog DPI Automation, Simulation Analyisis on Synopsys VCS.Definition of Initial TEST PLANS Specifications