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Robert Sibert Email & Phone Number
Senior Physical Designer at Acacia Communications Inc.
at
Marvell Semiconductor
2 work emails found
@microsemi.com
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
Senior Physical Designer at Acacia Communications Inc.
Location
Bethlehem, Pennsylvania, United States
Who is Robert Sibert? Overview
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Quick answer
Robert Sibert is listed as Senior Physical Designer at Acacia Communications Inc. at Marvell Semiconductor, based in Bethlehem, Pennsylvania, United States. AeroLeads shows a work email signal at microsemi.com and a matched LinkedIn profile for Robert Sibert.
Robert Sibert previously worked as Senior Physical Design Engineer at Cisco and Senior Physical Design Engineer at Marvell Semiconductor. Robert Sibert holds Electrical Engineering from Lafayette College.
Company email context
Email format at Marvell Semiconductor
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{first_initial}{last}@microsemi.com
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AeroLeads found 2 current-domain work email signals for Robert Sibert. Compare company email patterns before reaching out.
Profile bio
About Robert Sibert
Accomplished Physical Design Engineer with deep experience in the semiconductor industry, who adds value through innovation, commitment and attention to detail in cutting edge tech nodes.Specializing in complex physical design: floorplanning, layout, clock tree synthesis, low power design, physical verification, and STA.Cadence: Genus, Innovus, Tempus. Synopsys: ICC, Primetime Mentor: Calibre, Olympus, Nitro.Tool Sets: Cadence Innovus Cadence Tempus Mentor Graphics Calibre and Nitro/Olympus, Synopsys ICC Synopsys ICV.Available for contract or permanent staffing.Please connect or contact for resume.
Listed skills include Primetime, Perl, Compilers, Systems, and 19 others.
Current workplace
Robert Sibert's current company
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10 roles
Robert Sibert work experience
A career timeline built from the work history available for this profile.
Senior Physical Design Engineer
Current
Nov 2020 - Present
Senior Physical Design Engineer
Sub 10nm High Speed Custom Clocking development and scripting for top and sub hierarchies, with block layout assignments.
Sep 2019 - Sep 2020
Senior Physical Design Engineer
Digital Signal Processor: physical layout for high-speed, high-capacity optical networking applications for Submarine, Long-haul, and Metro transport, including Cloud/DCI.
Sep 2018 - Aug 2019
Staff Engineer (Support)
Successor to Centriq2400 - 7nm High Speed ARM Server Processor -- Physical Design, Chip top CTS, PVerf, ECO generation chip top, Floorplan to PVerf, MacroCentriq 2400 10nm 2.6GHz 48 core ARM Server Processor -- Physical Design, Chip top CTS, PVerf chip top, ECO generation and implementaionSnapdragon 820 2.2 GHz, 4x Kryo CPU -- Physical Design.
May 2014 - Aug 2018
Sr. Staff Mask Design Engineer (Customer Contract)
- Responsible for Place and Route on high-speed 22nm finFET processor.
- Responsible for four hierarchical blocks on radiation hardened FPGA, working on eight total plus top level integration of blocks.
- Assist in the development, improvement, and debug of Tcl scripts for block layout flow regarding clock tree synthesis, radiation hardening, reporting, outputs, spare cell insertion, etc.
- Documented/Proofed flow and procedures for local and international team members.
Jun 2013 - Apr 2014
Engineer Iii (Contract Via Xpeerant)
- Successfully completed challenging 28nm DSP for timing/power closure while meeting timing for all instantiated modules at top level.
- Evaluated floor plans for area reduction while maintaining critical timing paths, as well as addressing challenging congestion issues.
- Participated in layout tool evaluations for best outcomes in timing, congestion, run time, drc's.
Dec 2012 - Jun 2013
Physical Design Engineer
Aug 2012 - Nov 2012
Senior Physical Design Engineer
Lucent/Agere Systems from August 2000 to April 2007Physical Design Engineer
Aug 2000 - Feb 2012
Chemical Process Analyst
Lucent Technologies
MOS-V Class 10 Clean RoomSemiconductor Fab Processes: Chemical Clean, Oxidation/CVD, Photolithography, Ion Implantation, Plasma Etch and Metal Deposition
May 1998 - Aug 2000
2 education records
Robert Sibert education
Electrical Engineering
Lafayette College
Associates Degree, Electronic Engineering Technology
Lincoln Technical Institute
FAQ
Frequently asked questions about Robert Sibert
Quick answers generated from the profile data available on this page.
What company does Robert Sibert work for?
Robert Sibert works for Marvell Semiconductor.
What is Robert Sibert's role at Marvell Semiconductor?
Robert Sibert is listed as Senior Physical Designer at Acacia Communications Inc. at Marvell Semiconductor.
What is Robert Sibert's email address?
AeroLeads has found 2 work email signals at @microsemi.com for Robert Sibert at Marvell Semiconductor.
Where is Robert Sibert based?
Robert Sibert is based in Bethlehem, Pennsylvania, United States while working with Marvell Semiconductor.
What companies has Robert Sibert worked for?
Robert Sibert has worked for Marvell Semiconductor, Cisco, Acacia Communications Inc., Qualcomm, and Microsemi Corporation.
How can I contact Robert Sibert?
You can use AeroLeads to view verified contact signals for Robert Sibert at Marvell Semiconductor, including work email, phone, and LinkedIn data when available.
What schools did Robert Sibert attend?
Robert Sibert holds Electrical Engineering from Lafayette College.
What skills is Robert Sibert known for?
Robert Sibert is listed with skills including Primetime, Perl, Compilers, Systems, Drc, Clock Tree Synthesis, Lvs, and Physical Design.
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