Design Verification Engineer who thrives on complete ASIC development process from test bench development to extracting functional vectors. Deep understanding of test generation for system buses, cache coherency and I/O subsystems. Great ability in diagnosing to root cause on complex systems. Enjoys contributing in creative team environment.Selected Accomplishments* Developed diagnostics to pinpoint fabrication problems in the internal RAMs. Created and tested algorithm work around and then workstations shipped without needing fabrication fix.* Lead engineer responsible for overseeing the architecture of host-initiated DMA and MMU. Made architecture decisions on implementation of coherence transactions and clustering system transactions.* Designed server-driven, secure remote upgrade that was 99.6% successful for kiosk wireless router firmware. Monthly recurring savings was $45kSpecialties: SystemVerilog, SVA, Verilog, C++, Perl, Python, Debussy, VCS, ModelSim, Debussy