Bob Martell Email & Phone Number

Portland, Oregon Area

Performance Verification

Beaverton, Or

Managed $1.5M engineering budget for a medium sized companyBuilt an engineering team from the ground up and developed talent from entry level to lead contributor. Delivered technical sales team presentations. Worked with China consultants to source plastic and sheet metal tooling, castings, PCB assembly/testing and electrical componentsServed as principal technology expert: system architect, electrical design, power delivery, FCC/CE emission standards and automated testing for the following industrial printing products: Toro, Kodiak, Echo and RhinoSoftware Development Team Manager o Instituted an agile method of tightly coupled 2 week sprints. High quality product releaseso Developed an innovative automated software testing process. 30K+ tests run dailyo Researched, developed and verified an innovative supply security algorithmProduct Manager o Conducted competitive research to differentiate and improve product specs and costso Managed schedule, milestones and off site firmware deliveryo Kodiak 8.5in Color Thermal Transfer Printer (launched September 2017): Designed system architecture (2 core processor). Developed an innovative PCB pogo testing station and ribbon supply programming stationo Toro 4in Thermal Transfer Printer (launched May 2011): Designed XP Embedded OS, desktop shell, user interface and software spec for LabelForge. Integrated a 98WHr Li-ion battery; worked with a Taiwanese company and completed UN/CE certifications

Hillsboro, Or

o Principal engineer managing the i3/i5/i7 floor plan, power delivery and metal electromigrationo Managed a customer oriented fullchip team of 11 design automation engineers responsible for supporting a design team of over 100 mask designers and engineers. This encompassed understanding customer needs and a timely response to their issues. In addition, oversaw project schedule commitments and adjusted as necessaryProcess Interconnect Researcho Contributed to P858, P860, P1262, P1264, P1266 & P1268 process interconnect researcho Collected design team process fabrication requirements for each process. This included collecting full chip metal interconnect lengths, layer distributions, speeds and power delivery requirementso Organized the data into technical presentations to influence process interconnect decision makersConference Session Chairmano Appointed layout session chairman for 2 years. Reviewed technical papers and conference presentations o Authored 7 Intel conference papers. This included 2 best of session and one conference presentation

Hillsboro, Or

Managed the following design activities for the Pentium Pro Reservation Stationo Directed a team of 3 engineers and 4 mask designerso Owned the schedule of various milestones over a 3 year design cycleo Researched out-of-order execution and developed the technology: microarchitecture, RTL and circuits

Hillsboro, Or