A principal verification resource currently supporting frontend Verification for NXP

A principal verification resource assisting frontend ASIC or FPGA development teams

On site to General Dynamics Mission Systems, Scottsdale AZVerification of FPGA designs for satellite programsDeveloped tests and test benches for RTL using UVM and SystemVerilog

• Verification contributor and remote team lead• Support multiple concurrent SerDes programs• Migrate legacy SystemVerilog test infrastructure to UVM• Auditing legacy product verification readiness• Improving team processes and methodologies

• Verification of FPGA products for D.O.D. Satellite programs• Work with UVM (or UVM-lite) test benches using constrained random tests and runtime checkers• Designed runtime UVM models of DSP functions of the DVBS2 specification. This opened up our testing to randomized test generation, greatly surpassing our coverage using legacy bit-file comparison tests.• Involved throughout initial program planning, development, testing, and delivery• Audit verification coverage and specification thoroughness• Involved in process improvement - Server arm architecture; Design and Verification Reviews; Best practices; I.P. solutions

• Senior Verification contributor on JEDEC RCD02 ASIC development• Created UVM tests; Debug and failing legacy regressions• Supported the ATE group by modifying tests to characterize timing and functional requirements• Co-authored a DV Methodology document produced by our office as a best practices document for all DV within Inphi• Verified ‘Save’ and ‘Restore’ functionality of the JEDEC RCD02

• Worked in the same office for 11 years as the company changed hands twice• 2004 – 2009 with Intellon Corp• 2009 – 2011 with Atheros Corp• 2011 – 2015 with Qualcomm• Hired as the lead verification engineer in 2004, I built up a verification team of 10+ engineers.• Performed, and transitioned, as lead, architect, manager, senior staff• Transitioned the verification environment from the legacy Synopsys’ VERA, to UVM. All of which used randomized stimulus, and automatic, runtime checking.• As lead and Verification Architect, I designed and specified most of the VIP components, test benches, test plans, reviews, and checklists. Participated in, or owned, project planning, schedules, debugging issues, mentoring staff, process and methodology improvements.• Our products were PowerLine® SOC, until we transitioned to Qualcomm, at which point we worked on their product line.• Our PowerLine® SOC was a communication device with a transceiver adapted to the A/C lines in the US, Europe, and China. As such, it had an OFDM PHY for interfacing to the A/C, and various user interfaces such as Ethernet, MPEG etc. Between the two was an ARM processor with a custom fabric, memories, FLASH, Security, Test features, an Ethernet PHY, and so on.• I personally owned the verification efforts for BOOT ROM, Ethernet behavior as a PHY or MAC (auto-negotiation etc.), ARM processor throughput using a switch fabric, ARM peripheral components – Watch Dog timers, Interrupt Controllers and management, FLASH controllers, product reprogramming (using FLASH), GATE simulations, and many more I’m sure.• I owned or touched, most if not all, of the scripts used for simulation control, boot-ROM development and testing, source code management.

• Fabless semiconductor company building encryption engine IP in an SOC• Individual contributor; tested the PCI interface using SystemVerilog and Synopsys’ VERA• Company closed, or filed for bankruptcy

• Small OEM working via DARPA on encryption solutions• Board-level design for PC-based cards that accelerated encryption for software.• Designed control logic and FPGA’s

• D.O.D. company working on flight and underwater programs• Individual contributor: Designed, and tested board-level DSP functions that were part of a larger programs.• Developed test systems using off the shelf VME test equipment. C-based SW to exercise the controls and stimulus of deliverable component.