Robert Kellogg Email & Phone Number

Scottsdale, AZ, US

A principal verification resource currently supporting frontend Verification for NXP

Ottawa, Ontario, CA

A principal verification resource assisting frontend ASIC or FPGA development teams

Waltham, MA, US

On site to General Dynamics Mission Systems, Scottsdale AZVerification of FPGA designs for satellite programsDeveloped tests and test benches for RTL using UVM and SystemVerilog

Bangalore, Karnataka, IN

• Verification contributor and remote team lead
• Support multiple concurrent SerDes programs
• Migrate legacy SystemVerilog test infrastructure to UVM
• Auditing legacy product verification readiness
• Improving team processes and methodologies

Fairfax, VA, US

• Verification of FPGA products for D.O.D. Satellite programs
• Work with UVM (or UVM-lite) test benches using constrained random tests and runtime checkers
• Designed runtime UVM models of DSP functions of the DVBS2 specification. This opened up our testing to randomized test generation, greatly surpassing our coverage using legacy bit-file comparison tests.
• Involved throughout initial program planning, development, testing, and delivery
• Audit verification coverage and specification thoroughness
• Involved in process improvement - Server arm architecture; Design and Verification Reviews; Best practices; I.P. solutions

San Jose, California, US

• Senior Verification contributor on JEDEC RCD02 ASIC development
• Created UVM tests; Debug and failing legacy regressions
• Supported the ATE group by modifying tests to characterize timing and functional requirements
• Co-authored a DV Methodology document produced by our office as a best practices document for all DV within Inphi
• Verified ‘Save’ and ‘Restore’ functionality of the JEDEC RCD02

San Diego, CA, US

• Worked in the same office for 11 years as the company changed hands twice
• 2004 – 2009 with Intellon Corp
• 2009 – 2011 with Atheros Corp
• 2011 – 2015 with Qualcomm
• Hired as the lead verification engineer in 2004, I built up a verification team of 10+ engineers.
• Performed, and transitioned, as lead, architect, manager, senior staff

• Fabless semiconductor company building encryption engine IP in an SOC
• Individual contributor; tested the PCI interface using SystemVerilog and Synopsys’ VERA
• Company closed, or filed for bankruptcy

• Small OEM working via DARPA on encryption solutions
• Board-level design for PC-based cards that accelerated encryption for software.
• Designed control logic and FPGA’s

• D.O.D. company working on flight and underwater programs
• Individual contributor: Designed, and tested board-level DSP functions that were part of a larger programs.
• Developed test systems using off the shelf VME test equipment. C-based SW to exercise the controls and stimulus of deliverable component.