Roger Koehler Email & Phone Number

Salt Lake City, Ut, Us

Salt Lake City, Utah, United States

Greater Salt Lake City Area

• Upgraded Optical Transmitter circuit card design using Mentor Graphics DxDesigner• Upgraded Digital Modem VHDL for Bandwidth Efficient Common Data Link (BE-CDL) Rev B compliance• Designed and implemented HDLC framer with XAUI interface in VHDL for wireless communications application using Xilinx Virtex-6 FPGA.• Ported PLL design from Xilinx Virtex 2Pro to Altera Cyclone V FPGA• Converted RF Receiver and Digital Down Converter PCB from Virtex-2Pro to Kintex-7 FPGA w/ DDR3.

Greater Salt Lake City Area

Designed and supported engineered solutions for monitoring and inspecting essential piping systems.

• Updated modular (GeckoFlex) Network Interface Board with new PHY and assisted software engineers to update software interface and verify correct functionality with built-in test firmware.• Using Verilog HDL, generated RTL code for 3G video fiber optic interface board for high end (Trinix) router.• Verified FPGA designs using ModelTech Modelsim and Xilinx ChipScope.• Performed role of Scrum Master in progressive use of Scrum agile development methodology for hardware design.

• Provided technical leadership on ground based radar program for digital receiver/transmitter dual FPGA SoC (System on Chip) design using Xilinx Virtex-4 for direct digital synthesis of LFM transmission waveform and Virtex-5 for digitally basebanding, filtering, decimating, and transmitting the processed digital samples over high speed 2.5 Gbps serial Front Panel Data Port (sFPDP) using Xilinx high speed serial transceivers and embedded Microblaze processors and associated software/firmware in C programming language and Xilinx EDK (embedded development kit).• Designed direct digital synthesis (DDS) printed circuit card (PCB) layout and assembly including high speed differential routing of 800 MHz DAC clock input signal, 400 MHz DAC output clock, and 400 Mbps digital data (DDR) to the Virtex-4 FPGA.• Provided proposal input on firmware design cost and schedule using Microsoft Powerpoint presentations and Excell spreadsheets.• Tracked requirements using DOORS.• Generated circuit description documents (CDDs) for the DDS and Receiver FPGA designs using Microsoft Word and Visio.• Debugged design using Agilent logic analyzer, Xilinx Chipscope, Agilent spectrum analyzer, Tectronix digital oscilloscopes, and HP signal generators.• Used VHDL and Xilinx CoreGen for firmware design and simulated using ModelTech ModelSim.

Provo, Utah Area

Developed large FPGA designs using Verilog HDL for ASIC prototyping and emulation of QPSK modem and proprietary network targeted for high temperature environments.

Developed board level hardware and embedded software using PCAD, C/C++ and assembly language for central lighting control processing unit and low-power distributed control unit with back-lit buttons and IR interface.

Began electrical engineering career at Evans and Sutherland Computer Corporation as Hardware Engineer I. Performed board level and FPGA (programmable logic) level design functions.

Received internship at Evans and Sutherland Computer Corporation while attending the University of Utah. Worked in Components Engineering developing and improving component description and tracking.

Served in the United State Air Force during Gulf War as Avionics Technician bench testing and repairing Avionics Equipment used on A-10 and F-16 aircraft.

Bachelor Of Science, Electrical Engineering

Associate Of Arts, General Study

Associate Of Science, Avionics Technology