Roger Carpenter Email & Phone Number

Mountain View, CA, US

https://cloud.google.com/tpu

San Jose, California(CA), US

- Architectural exploration of next machine learning accelerator including matrix multiplication and 2D convolution.- Prototype future machine learning products on FPGA using external vendor for design implementation.- Determine Network on Chip (NoC) and interface IP including HBM, HMC, DDR, PCIe, Interlaken, and CCIX.- Manage 16nm FinFET physical and.

- Responsible for design services of sequential clock gating and power pattern generation products. - Design adaptive voltage scaling (AVS) IP including embedded low dropout (LDO) regulators. - Report account engagement strategy, technical execution, investment strategy at board meetings.

- Manage R&D team sprints, scrums. Extend roadmap: ESL, floorplan synthesis, cloud computing. - Partner with IMEC and Qualcomm: Develop architecture and 3D TSV Pathfinding methodology. - Manage and extend customer relationships with presentation, support, training, design services.

Mountain View, CA, US

- Drove strategic growth of company from single core product to multiple distinct business units. - Galvanize technical sales execution of critical accounts in order to meet quarterly revenue targets. - Manage power gating, hierarchy automation, structured placement, package/chip design teams. - Manage developers and support engineers globally including.

Palo Alto, California, US

- Managed design groups totaling 15 engineers and up to six projects. Outsourced acquired design. - Project management of 12 unique Ethernet switches across physical, logic, test, and verification. - Established implementation and signoff methodology including clock, DDR, OCV, and crosstalk.

Mountain View, CA, US

- Established initial physical synthesis flow from logic synthesis through post layout optimization. - Managed team of seven product and design engineers across multiple customers and disciplines. - Customer and internal management of largest tapeout to date at 3Dlabs (Nov 2000 press release)

US

- Designed and characterized standard cell library. Floorplan, place, and route methodology. - Assisted in design of high speed 4-read/4-write memory and custom datapath arithmetic blocks. - Created signoff methodology including extraction and crosstalk analysis. Implemented clocks.

San Jose, CA, US

- Top-down FPGA chip design using Synopsys logic synthesis and Cadence layout synthesis. - I/O cell design, interconnect and test strategies. Look up table vs. antifuse architecture tradeoffs. - Voltage pump and voltage regulator design. Critical path optimization with spice and STA.

- SOI fully depleted device modeling, add back-bias to speedup EEPROM GAL.

- X-ray lithography triboepitaxial thin film crystalline silicon with C control

- Test vehicles for BiCMOS standard cells and gate arrays.

Cambridge, Massachusetts, US

- Graphics and virtual reality optical sensor hand recognition: assembly, C.

Master Of Science (M.S.), Electrical Engineering And Computer Science

Bachelor Of Science (Bs), Electrical Engineering And Computer Science