Rohith N Email & Phone Number

United States

Performed analog/logic/functional validation in post-silicon and pre-silicon environments.Utilized Verilog/SV for hardware design verification and Python for scripting automated test procedures.Implemented DFT/DFD techniques to enhance testability and fault coverage of SOC designs. Collaborated with design engineers to troubleshoot and resolve functional anomalies identified during validation.Contributed to the development of new test methodologies and optimization of existing test processes.

India

Performed all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure for high-speed CPU core designsDeveloped strategies to achieve reproducible design convergence results, resulting in improved efficiency and reduced design cycle times.Collaborated with the design team to create and refine synthesis flows, enhancing overall design quality and predictability.Implemented best practices for physical design, including floorplanning, routing techniques, clock distribution, static timing analysis, noise analysis, and reliability verification.Utilized scripting languages (TCL, Python) to automate repetitive tasks and streamline the design process.

Master Of Science - Ms, Electrical And Electronics Engineering, 3.589

Bachelor Of Technology - Btech, Electrical And Electronics Engineering, 8.78 Gpa