Ron Kee Email & Phone Number

Palo Alto, California, Us

On October 19th, I officially joined the ranks of the "Retired". I was very fortunate to work 39 yrs at HP (Fort Collins, CO and Corvallis, OR), Agilent Technologies, Avago, and Broadcom Inc. I've left a great team of engineers and technicians that I had the privilege to grow and manage over the past 18 yrs. I will certainly miss the daily interaction and the responsibilities of my Labs manager position, but know that my team will continue to grow and succeed with Broadcom. I know that I will not be bored in retirement, but will have the opportunity to be more fully engaged with our family and friends as we make the most of this season of life.

Palo Alto, California, Us

Engineering Manager for a team of 16 (engineers and technicians), with some contracted lab technicians. We provide R&D, Mfg, and Qualification support for multiple Broadcom BU's, using REL equipment and Analytical instrumentation in our World Class Analytical / Reliability support Labs and our ASIC ATE Test facility. These Lab areas provide for the semiconductor PA, FA, and REL stressing of semiconductor wafers and ASIC products. In our ATE Test facility, we have Advantest (Verigy) ATE Testers...93K PinScale, 93K PS400B (UHC4), and the latest 93K SmartScale PS1600. The main Physical Analysis Lab is staffed 7 days/week, supporting the two on-site WSD wafer FAB's (Si and GaAs fabs), and the APD ASIC Design Center. In our REL Labs, we provide "Best in Class" Biased ASIC Product Reliability stressing for the various Classic Avago, xLSI, and multiple Broadcom BU's. We are now Broadcom, Inc, a U.S. based company.

San Jose, Ca, Us

R&D Engineering Manager for a team of 17 engineers, technicians, and contracted workers. We provide R&D, Mfg, and Product Qualification support, using equipment and instrumentation in our three World Class Analytical / Reliability support Labs and our ATE Test facility. These Lab areas provide for semiconductor Physical Analysis, Failure Analysis, FIB Circuit Editing, and Environmental Stressing. In our ATE Test facility, we have Advantest ATE Testers...93K PinScale / TEL P12 prober, 93K UHC4, and a new 93K PS1600. The main Labs are staffed 7 days/week, supporting the two on-site Avago Divisions...the WSD wafer FAB's (Si and GaAs fabs), and the APD ASIC Design Center. For the ASIC Design Center, we've advanced our FIB circuit editing to be a World Class leader in the technology. In our REL Labs, we provide "Best in Class" Biased ASIC Product Reliability stressing for the various Avago Business Units (Avago and xLSI).

Santa Clara, Ca, Us

Senior Electrical Engineer supporting the Analysis Labs in Ft. Collins, CO, until Feb 2001. The HP company was split in 2000, into HP and Agilent Technologies and I became an employee of Agilent. After workforce reductions and re-organizations, I accepted the FA Engineering Management position for the Analysis Labs, in Feb 2001, which began my return into R&D Engineering Management of engineers and technicians.

Houston, Texas, Us

20 year veteran of HP, starting with the IC Division (STO) in Ft. Collins for almost 2 yrs, before transferring to HP-Corvallis, OR. I worked 17 years in Corvallis with the IC Division (ICBD), working in the PA/FA Labs as both an Engineer and the Labs Manager, in support of the IC and Inkjet FABs, and the HP calculator /PC product lines. HP's IC Operations were consolidated to Ft Collins, CO and I accepted a company transfer to move back in September 1998. As the Senior Lab Engineer, I was responsible for the design and construction of the new Analysis Labs (PA and FA Labs) in Ft. Collins, the spring/summer of 1998, and the purchase of all the major lab equipment. This was a $5M project that was completed in early August 1998.

Msee, Semiconductor Technology / Device Physics

High School Diploma, Math And Science