Ronak Bajaj Email and Phone Number

- Building LPDDR5/5X Memory Controller

- Worked on implementing Safety critical computation platforms- Design Lead for a sub-system within SOC, working on development and integration of ISO 26262 ASIL-D compliant design- Worked on sub-system's architecture and integration; designing and configuring Arteris FlexNoC- Involved in architecture and design reviews, RTL implementation, verification plan, physical design plan- Managed team of 6+ engineers working on execution of the sub-system

-Worked on Cloud FPGA and compute instances (AWS F1, Azure NP) to accelerate database queries. Lead product migration from on-prem to cloud FPGAs. - Lead RTL development of rENIAC Data Engine and worked on developing designs for efficient implementation of rENIAC Storage Engine- Closely worked with Hardware, Software, and Devops teams to execute the product from conception to production- Executed the products on cloud platforms for hybrid Software-FPGA model, overcoming many challenges of relatively newer platforms for FPGAs to extracting maximum performance for Apache and DSE Cassandra workloads

- Worked on accelerating operations for distributed database systems.- Developed a high throughput on-the-fly parallel data shuffling for OpenCL based implementations. Platform: CPU+FPGA hybrid architectures with OpenCL.- Managed PhD students and other Researchers

- Head of product development - focusing on product roadmap and development of the cloud based urban intelligence platform for smart cities.- Worked on developing an immersive 3D audio solution for virtual and augmented reality applications.

- Member of EF's first cohort in Singapore.- Conceptualized the idea and started Immerzen Labs company.

Implemented Secure Hash Algorithm (SHA) variants for FPGAs and ASIC.Worked on designing SHA implementation on Tensilica Xtensa, with custom instructions to accelerate SHA.ASIC toolchain setup.

Developed an automated tool flow that takes a high-level description of a computational kernel in C and generates different synthesizable Verilog implementations, achieving performance close to theoretical limits of FPGA hardware.Mapping for Maximum Performance on FPGA DSP Blocks: Developed techniques and tool chain for mapping computationally intensive applications described in C/C++ onto FPGAs, exploiting full functionalities of DSP blocks to achieve performance of design close to theoretical maximum throughput of DSP blocks.Initiation Interval Aware Resource Sharing: Developed techniques to implement a design with minimum resource requirement while achieving an input throughput constraint. These techniques unlock a large design space which is generally not accessible using traditional techniques. Integrated developed techniques into tool flow.Multi-pumping DSP Blocks for Resource Sharing: Running DSP blocks at double the frequency of system can reduce the usage by half. Developed three different scheduling techniques for implementing designs using multi-pumped DSP blocks. DSP block utilization is reduced to half without an increase in initiation interval.

Graduate Teaching Assistant for various undergraduate and graduate level courses in School of Computer Science and EngineeringDigital Systems Design (CE2003), undergraduate, Sem1 AY2014-15Digital Logic (CE1005), undergraduate, Sem2 AY2014-15Advanced Computer Architecture (CE3001), undergraduate, Sem1 AY2015-16Advanced Computer Architecture (CE3001), undergraduate, Sem2 AY2015-16Computer Organization and Architecture (CE1006), undergraduate, Sem2 AY2015-16Algorithms to Architectures (ES6126), graduate, Sem2 AY2015-16

Designed and implemented architectures for network protocols on NetFPGA board. Used AutoESL’s AutoPilot high-level synthesis tool for C++ implementation.

Student Placement Lead for 2010 Graduating Batch

Teaching Assistant for various undergraduate and graduate level courses.Digital Logic and Processors, undergraduate, Sem1 AY2009-10Digital Design with HDLs, graduate, Sem2 AY2009-10

Responsibilities included generating sponsorships, maintaining records of all financial transactions of iRC, and planning funds allocation for iRC conducted events.

Member of the organizing and technical team of two editions of RoboCamp'08, a national level robotics workshop at IIIT-H (June 2008) and a state level workshop at KIET, Kakinada (Aug 2008).Responsibilities included bringing in top-class robotics faculty to offer talks and mentoring participants to enable them build robots from the scratch.

Summer internship at Center for VLSI and Embedded System Technologies (CVEST), IIIT-H under the guidance of Dr. M. B. Srinivas.