Ronald Freking Email & Phone Number

Brooklyn Park, Minnesota, United States

Design, verify and lab test ASICs.

Bothell, Washington, United States

Develop Xilinx FPGA designs, space radios and DSP features.

Greater Minneapolis-St. Paul Area

Designed, verified and maintained a large scale FPGA design.Use RFSOC Xilinx tools to create a digital signal canceller.

Greater Minneapolis-St. Paul Area

ASIC and FPGA design and verification.

Greater Minneapolis-St. Paul Area

ASIC Design for Memory Devices

Greater Seattle Area

Responsibilities:* Design and architect monochrome ISP / Depth sensor ISP* Architect multiple pixel pipeline color ISP* Architect and design image display pipeline* Code C++ model for architecture designsAchievements:* Architect IP for Hololens* Translate color ISP C++ pipeline to silicon architecture* Architect vendor IP for SoCs

Greater Seattle Area

Responsibilities:* Implement verilog memory transfer system for ISPs* Design and verify verilog IP* Sensor control system for ASIC / SoC* Resolve timing issues through synthesisAchievements:* Design IP for Hololens in verilog* Work with sensor control for Hololens* Understanding machine learning and Augmented Reality

Rochester, Minnesota

Responsibilities:* Architect and design IP for server applications* Lead 2-8 people in effort to create IP* Manage schedule of design effort to create IP* Implement and verify IP in VHDL* Manage synthesis for large IP in silicon designAchievements:* Advanced knowledge of VHDL and PERL* Create PCIe Gen-2 and Gen-3 application layers* Fabric connection to.

Rochester, Minnesota

Responsibilities:* Design VHDL for IP in server applications* Verify VHDL designs* Use scripting languages to make verification and design simplified* Synthesis and timing of VHDL IPAchievements:* Patents and silicon for PCIe* Patents and silicon for DDR memory controllers* Patents and silicon for Power PC cores* Silicon design of scaling processors, North.

Rochester, Minnesota

Responsibilities:* Design and verification of VHDL silicon Designs* Use scripting to improve logic verification* Timing and synthesis of VHDLAchievements:* Develop system to speed up verification via scripts* PCIe and DDR controller design and verification* Familiarity with IBM toolsets

Bs, Electrical And Computer Engineering

Ba, Applied Physics