IC Design flow automation.- RTL to GDS Design flow automation.- IO/Bumps/ESD/MIMcap placements and planning algorithms- Tapeout signoff PDV checks.- Custom Macro/IP layout design and integration.Software developing- Python, Tcl, Shell programming Using GitLab and VsCode.

Custom digital and mix signal layout manager.Chip level layout floorplan and Integration.Custom clocking flow.Automated Bump flow.Physical Design Verification flow.Custom CAD manager.Tapeout and signoff.

- Successfully taped out 32 core ARM processor in FinFet technology.- Successfully tapes out multiple industry standard mixed signal connectivity chips in multiple process nodes. - Manage small extremely efficient and energetic team across multiple sites and time zones.- Manage and support custom CAD activities to improve productivity.- Activities:- - Methodology, integration and tapeout of Analog and Digital chips.- - Physical Design Verification flows definition and implementation.- - Semi custom High speed clock methodology and design from PLL to flops.- - Layout flows and Automation management.- - Tapeout and Job Views.- - Waiver and productivity flows definitions and development.- - Memories design layout management.- - Complex Standard cells layout and QA management.- - Complex mix signal integration and PDV support through tapeout.

Network large Chip Integration.Datapath pre-route implementation scripts. Full chip routing.Clock routing and balancing.Bump wiring and balancing.Final tapeout PDV checks.

Large Processor Chip Integration.Clock routing and balancing.Bump planning and wiring.VIA generator to improve Chip IR.Final tapeout PDV checks.

- IO custom cell floor planning and detailed layout.- IO slice floor planning and routing.- PDV clean takeout quality layout delivery.

Custom macro floor plan and layout.PDV clean block delivery.

ALU floor plan and layout.Block integration.PDV clean takeout quality block delivery.