Core member of team adding features to automatic API fuzzing and testing platform from Rust-written command line fuzzing tool to Rust-based backend, web frontend, and dev ops. Central role in hoisting authentication out of the existing Rust Actix+Diesel backend and into Keycloak, a separate authentication service, and deploying into Kubernetes clusters.Implemented key aspects of the Rust-based GraphQL API fuzz tester, including GraphQL specification ingestion, backend results communication and telemetry, and fuzzing of graphql data inputs.

Wrote a command line tool to automate creation of a new developer environment spanning AWS compute instances, AWS load balancers, multiple shared testing services, local machine, and Visual Studio. Previously, new hires would take between 1 and 2.5 weeks to get their developer environment setup due to the complexities of the software service oriented architecture. The updated automation flow could start a new developer environment in less than one hour, with approximately 3 minutes of command line prompt interaction with the user. After the updated flow, one new hire said, “I’ve never had a working development system this quick – this is amazing.”Fixed bugs and documented complicated user flows passing through upwards of 5 different services.

Created the https://qc.superapple.com platform to collect, organize, and display Kershaw quality control data. Due to the platform’s flexibility, it has since grown to encompass much more. At its core lies a Django REST server with tendrils into numerous data silos. Using Qt, C++, and React, wrote front-end clients for Android, Windows, Raspberry Pi, and the browser to collect sweetness, crispiness, pest damage, aromatics, time punch data, bin picking data, picker GPS location, and much more. Interfaced with many different external sensors to speed collection and accuracy of data. Data is finely-permissioned to protect Kershaw Fruit and our business partners. Wrote many views into the collected and siphoned data to make it accessible. Wrote a massive custom inventory instruction management tool to direct the ~$1 billion packing line infrastructure. Multiple live dashboards, monitors, and “Key Production Indicator” pages to provide actionable information at a glance. Created views into temperature, humidity, wind, soil moisture, farm “block” locations, irrigation maps, notes, and other data overlaid onto Google maps or displayed in tabular format with options to export into other formats. Built email notification and escalation systems flow control for time-critical events. Wrote many other views and assisted other workflows. Worked on arduino-based temperature, humidity, and soil moisture sensors. Worked on arduino truck fleet trackers that plugged into the ODB2 sensor and sent back data to the main office to track location and speed of trucks.Other duties include Linux servers maintenance, writing Traceability Tools for GS1-128 validation, legacy workflow sites, custom payroll site, various data system event processing and propagation, database curation, visually assisted data mapping, and workflow websites. Wrote application in Qt and C++ using OpenCV and CGAL to automatically find apples on a standard tray and then grade them.

Core member of simulation testbench software team to support 400 engineers executing across Intel's Many Integrated Core line of products.• Integrated fundamental message passing C++ verification IP into testbench. Improved vendor’s reuse flow by transitioning them to git and a more rigorous code patching methodology.• Supported users on six sites in five different time zones with their usage of the message passing checker and BFM IP.• Drove simulation performance through weekly profiles using six different profile tools and posted results on the intranet. Implemented refactorings to improve simulation speed by 71%, saving the project ~6 compute years of server time per week of the project.

• Verification technical lead for ring network fabric and distributed cacheline coherency tag directory (DTD). Technical lead in charge of checker infrastructure and coverage-based random sequence testing. Authored ~60% of the verification collateral for these test subjects.Identified that build flows were too slow and rewrote the flow in SCons to be 78% faster while supporting modular inheritance-based build derivatives for the 100+ different simulation models on the project. Vastly reduced the size, complexity, and inconsistency of the set of build targets. • Enabled parallel building of all steps either locally or on multiple machines. Implemented build flow user feedback in the form of target dependency graphs, report web pages, and build dependency timing diagrams.• Authored and implemented reuse protocol for sharing verification IP between two projects to avoid forking efforts too early.• Implemented outlook script to rewrite incomprehensible internal emails into a useful form.• Authored and supported the network layer of project-critical packet-level modeling and checking infrastructure.

• Worked as right-hand man of fullchip technical lead to help create and maintain a fullchip testbench for billion gate design. Wrote modeling and cross-checking components in C++, SystemC, and Specman. Created and maintained various memory pre-loading methods and supported hashing and memory interleaving transforms including clarifying and enhancing provided documentation and implementing functions in C++ and Specman for test writers and checker writers.• Authored checkers for verifying complex interleaved ring-network with virtual channels. Verified the ring-network with random and directed-random tests.• Used formal verification techniques to validate message class reservations on ring network in order to exhaustively verify specific anti-deadlock properties of the ring network.• Wrote and maintained python script to convert XML descriptions of control registers into verification components for all control registers in billion-gate chip with a 50 times speed improvement over the previous implementation.

• Responsible for inserting compression DFT logic on 17 blocks and provided feedback to block designers on testability issues. Scripted flow using Make, Perl, Python, BASH, and Matlab. Improved flow through use of assertions, data parsing and analysis, and various refactorings. Distributed flow to other engineers and then supported it.• Verified JTAG functionality on printer chip. Verified RAM BIST functionality through JTAG interface. Scripted mapping of vector re-simulation mis-compares onto original vectors to speed debugging process. Documented and distributed script to other engineers.• Created and simulated functional vectors to test DLL for printer chip. Collaborated with product engineering to get vectors working on silicon.• Implemented ECO's on printer ASSP per 3 party's specification and then verified RTL to Pre-Layout and Pre-Layout to Post-Layout using Cadence's LEC. Partially scripted extraction of ECO commands to decrease injection of human translation errors.

• Created test circuits as part of a team for needs of mechanical engineering team. Designed, implemented, tested, and documented connectivity verification circuit for mechanically flexing data/power link to robotic tape manipulator. Designed, implemented, tested, and documented circuitry to exercise solenoid with sensor feedback, RS-232 data logging, and LCD output using Microchip's PIC18F4550 MCU.•• Provided hardware support to the engineering team on the Scalar i500 tape library. Reworked PCBs of the Scalar i500 to implement hardware design changes and repair damaged hardware.•• Tested software and hardware in the firmware test team. Used automation methods involving Perl, IBM's Rational Robot, and in-house programs to stress test the Scalar i500. Documented interaction using MKS Integrity.