Anti counterfeiting logic design

[Through Marvell's acquisition of Avago's imaging business unit] As a key technical contributor, I architected, designed and verified IP blocks and subsystems for > 10 SoCs (from 250nm to 28nm), targeted at printer application including:- Custom instruction Tensilica CPUs for accelerating resolution enhancement algorithms- Imaging blocks for printing, including halftoning, rasterized image decompression, color space conversion and image scaling- Cryptographic acceleration engines for IPSec- Consumable (ink & toner) metering & enforcement for printers- AXI bus fabrics & CPU memory fabrics- Configurable high performance AXI based DMA engines for imaging pipelines- ARM CPU integration on multiple ASICs- Configurable & reusable components including queues, FIFOs, bus bridges etcI collaborated with software engineers, system architects, technical marketing & customers to ensure that the products & interfaces delivered the right mix of performance, cost & usability.

[Through Avago's purchase of Agilent's semiconductor business unit]See Marvell section for position details

See Marvell section for position details

[Through Ericsson's acquisition of Qualcomm Infrastructure business unit]

Designed a router subsystem for a next generation CDMA basestation, , including board design, FPGA design in VHDL & bringup

Designed and implemented wireless LAN systems using the DECT protocol