Ramesh S Email & Phone Number

Bengaluru, KA, IN

Bengaluru, Karnataka, India

Managing RTL, Digital verification, MSV, FE verification team for DDR PHY IP for data centre products.

Bangalore

Defining architecture for HBM memory controller(Hbm2e -2.8 GTS and 3.2 GTS) for data center products and data center accelarators.- Defining functional Architecture from JEDEC specification and customer requirements. - Analysing performance feedback and incorporating in architecture. - Defining structure sizes - Defining programming interfaces and register.

Bangalore Area, India

Managing logic and validation teams for IPs Gen3phy Serdes, hbmio, gpio and DDR5 subsystem

Bangalore Area, India

Micro-architecting the digital logic required in Server micro processors. Focussed on DDR memory controller.- Defining micro architecture from specification. - RTL coding using system Verilog. - Initial design validation using test benches. - simulation using VCS. - First run synthesis using DC. - guiding backend team in pin placement, macro placement..

micro-architecting the digital logic required in Cryptography IPs

B.E, Electronics And Communication

Education record

Education record